aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/display (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-08-27drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of encoder->typeManasi Navare1-1/+1
2019-08-27drm/i915: Do not create a new max_bpc prop for MST connectorsVille Syrjälä1-1/+9
2019-08-21drm/i915: Fix HW readout for crtc_clock in HDMI modeImre Deak1-2/+2
2019-08-05drm/i915: Fix wrong escape clock divisor init for GLKStanislav Lisovskiy1-2/+2
2019-08-05drm/i915: fix possible memory leak in intel_hdcp_auth_downstream()Wei Yongjun1-1/+2
2019-07-29drm/i915: Fix the TBT AUX power well enablingImre Deak1-2/+9
2019-07-29drm/i915/vbt: Fix VBT parsing for the PSR sectionDhinakaran Pandiyan2-4/+4
2019-07-29drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHVVille Syrjälä1-0/+11
2019-07-29drm/i915: Deal with machines that expose less than three QGV pointsVille Syrjälä1-5/+10
2019-07-29drm/i915: Fix various tracepoints for gen2Ville Syrjälä1-2/+2
2019-07-25drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva2-1/+2
2019-06-21Merge tag 'drm-intel-next-2019-06-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie103-0/+90176
2019-06-18drm/i915/psr: Force manual PSR exit in older gensJosé Roberto de Souza1-10/+26
2019-06-18drm/i915: Drop the _INCOMPLETE for has_infoframeVille Syrjälä1-1/+1
2019-06-18drm/i915: Make pipe_config_err() vs. fastset less confusingVille Syrjälä1-79/+79
2019-06-18drm/i915: Constify intel_pipe_config_compare()Ville Syrjälä1-26/+17
2019-06-18drm/i915: Don't clobber M/N values during fastset checkVille Syrjälä1-8/+28
2019-06-18drm/i915: Use drm_gem_object.resvChris Wilson1-3/+3
2019-06-17drm/i915/ehl: Introduce Mule Creek Canyon PCHMatt Roper4-4/+50
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula56-1/+51785
2019-06-17drm/i915: move modesetting output/encoder code under display/Jani Nikula48-0/+38313
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.