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path: root/drivers/gpu/drm/i915/display (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-09-29drm/i915: constify hotplug function vtable.Dave Airlie1-2/+2
2021-09-29drm/i915: constify fdi link training vtableDave Airlie1-4/+16
2021-09-29drm/i915: split the dpll clock compute out from display vtable.Dave Airlie2-11/+11
2021-09-29drm/i915: split fdi link training from display vtable.Dave Airlie1-4/+4
2021-09-29drm/i915: split irq hotplug function from display vtableDave Airlie1-2/+2
2021-09-29drm/i915: split cdclk functions from display vtable.Dave Airlie1-71/+71
2021-09-29drm/i915: split audio functions from display vtableDave Airlie1-12/+12
2021-09-29drm/i915: split color functions from display vtableDave Airlie1-32/+32
2021-09-29drm/i915: split watermark vfuncs from display vtable.Dave Airlie1-17/+17
2021-09-29drm/i915/display: add intel_fdi_link_train wrapper.Dave Airlie3-1/+11
2021-09-29drm/i915: add wrappers around cdclk vtable funcs.Dave Airlie4-11/+44
2021-09-29drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)Dave Airlie1-62/+123
2021-09-29drm/i915: make update_wm take a dev_priv.Dave Airlie1-5/+5
2021-09-28drm/i915/display: Fix the dsc check while selecting min_cdclkVandita Kulkarni1-6/+4
2021-09-27drm/i915/audio: Use BIOS provided value for RKL HDA linkKai-Heng Feng1-2/+3
2021-09-24drm/i915/fbc: Allow higher compression limits on FBC1Ville Syrjälä1-13/+7
2021-09-24drm/i915/fbc: Implement Wa_16011863758 for icl+Ville Syrjälä1-2/+10
2021-09-24drm/i915/fbc: Align FBC segments to 512B on glk+Ville Syrjälä1-3/+11
2021-09-24drm/i915/fbc: Rework cfb stride/size calculationsVille Syrjälä1-59/+121
2021-09-23drm/i915/display: Only keep PSR enabled if there is active planesJosé Roberto de Souza7-80/+98
2021-09-23drm/i915/display: Match PSR2 selective fetch sequences with specificationJosé Roberto de Souza5-19/+36
2021-09-23drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware loadJosé Roberto de Souza1-13/+3
2021-09-23drm/i915/adlp: Add support for remapping CCS FBsImre Deak3-42/+58
2021-09-23drm/i915: Follow a new->old platform check order in intel_fb_stride_alignmentImre Deak1-8/+8
2021-09-23drm/i915/adlp: Assert that VMAs in DPT start at 0Imre Deak1-0/+5
2021-09-23drm/i915/adlp: Require always a power-of-two sized CCS surface strideImre Deak1-4/+30
2021-09-23drm/i915: Use tile block based dimensions for CCS origin x, y checkImre Deak1-5/+25
2021-09-22drm/i915: s/crtc_state/new_crtc_state/ etc.Ville Syrjälä1-19/+19
2021-09-22drm/i915/display: Add HDR mode helper functionTejas Upadhyay1-3/+7
2021-09-20drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132bJani Nikula1-0/+11
2021-09-20drm/i915/dg2: use 128b/132b transcoder DDI modeJani Nikula1-7/+20
2021-09-20drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0Jani Nikula1-1/+16
2021-09-20drm/i915/dp: select 128b/132b channel encoding for UHBR ratesJani Nikula1-1/+2
2021-09-20drm/i915/dp: use 128b/132b TPS2 for UHBR+ link ratesJani Nikula1-3/+7
2021-09-20drm/i915/dp: add helper for checking for UHBR link rateJani Nikula2-0/+7
2021-09-20drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b modeJani Nikula1-3/+3
2021-09-17drm/i915/display/adlp: Add new PSR2 workaroundsJosé Roberto de Souza1-1/+26
2021-09-17drm/i915/display/psr: Use drm damage helpers to calculate plane damaged areaJosé Roberto de Souza1-24/+13
2021-09-17drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabledJosé Roberto de Souza1-0/+25
2021-09-17drm/i915/display: Wait at least 2 frames before selective updateJosé Roberto de Souza1-1/+1
2021-09-17drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculationJosé Roberto de Souza1-1/+1
2021-09-17drm/i915/dmc: Update to DMC v2.12Anusha Srivatsa1-2/+2
2021-09-16drm/i915: Free all DMC payloadsChris Wilson1-1/+4
2021-09-15drm/i915: Update memory bandwidth parametersRadhakrishna Sripada1-3/+16
2021-09-15drm/i915: Extract hsw_panel_transcoders()Ville Syrjälä1-5/+11
2021-09-15drm/i915: Adjust intel_dsc_power_domain() calling conventionVille Syrjälä3-45/+44
2021-09-15drm/i915: Introduce with_intel_display_power_if_enabled()Ville Syrjälä1-0/+4
2021-09-15drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONFVille Syrjälä9-36/+36
2021-09-15drm/i915: Flatten hsw_crtc_compute_clock()Ville Syrjälä1-9/+11
2021-09-15drm/i915: Extract intel_dp_need_bigjoiner()Ville Syrjälä1-5/+14
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