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path: root/drivers/gpu/drm/i915/display
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2022-03-15drm/i915: Introduce intel_panel_get_modes()Ville Syrjälä6-52/+24
2022-03-15drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä8-23/+55
2022-03-15drm/i915: Nuke dev_priv->drrs.typeVille Syrjälä2-7/+5
2022-03-15drm/i915: Simplify intel_panel_info()Ville Syrjälä1-15/+9
2022-03-15drm/i915/lvds: Pass fixed_mode to compute_is_dual_link_lvds()Ville Syrjälä1-3/+4
2022-03-15drm/i915/sdvo: Pass the requesed mode to intel_sdvo_create_preferred_input_timing()Ville Syrjälä1-11/+7
2022-03-15drm/i915/dsi: Pass fixed_mode to *_dsi_add_properties()Ville Syrjälä2-9/+11
2022-03-14drm/i915/display/adlp: Update eDP voltage swing tableJosé Roberto de Souza1-2/+16
2022-03-10drm/i915: Rename PIPECONF refresh select bitsVille Syrjälä1-2/+2
2022-03-10drm/i915: Clean up DRRS refresh rate enumVille Syrjälä2-38/+24
2022-03-10drm/i915: Polish drrs type enumVille Syrjälä3-11/+11
2022-03-10drm/i915: Program MSA timing delay on ilk/snb/ivbVille Syrjälä3-2/+10
2022-03-10drm/i915: Read DRRS MSA timing delay from VBTVille Syrjälä1-0/+3
2022-03-10drm/i915: Pimp DRRS debugsVille Syrjälä1-5/+13
2022-03-10drm/i915: Constify intel_drrs_init() argsVille Syrjälä2-2/+2
2022-03-10drm/i915: Fix up some DRRS type checksVille Syrjälä1-2/+2
2022-03-10drm/i915: Remove struct dp_link_dpllVille Syrjälä1-38/+17
2022-03-10drm/i915: Populate bxt/glk DPLL clock limits a bit moreVille Syrjälä1-2/+1
2022-03-10drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()Ville Syrjälä1-10/+13
2022-03-10drm/i915: Replace bxt_clk_div with struct dpllVille Syrjälä1-34/+16
2022-03-10drm/i915: Store the m2 divider as a whole in bxt_clk_divVille Syrjälä1-14/+13
2022-03-10drm/i915: Clean up bxt/glk PLL registersVille Syrjälä1-16/+16
2022-03-10drm/i915: Remove redundant/wrong commentsVille Syrjälä1-10/+5
2022-03-10drm/i915: Store the /5 target clock in struct dpll on vlv/chvVille Syrjälä1-13/+10
2022-03-10drm/i915: Make the PIPESRC rect relative to the entire bigjoiner areaVille Syrjälä4-18/+40
2022-03-09drm/i915/dsi: use min_t() to make code cleanerChangcheng Deng1-4/+1
2022-03-08drm/i915: Fix the async flip wm0/ddb optimizationVille Syrjälä5-25/+31
2022-03-08drm/i915: Check async flip capability early onVille Syrjälä1-7/+72
2022-03-08drm/i915: Avoid negative shift due to bigjoiner_pipes==0Ville Syrjälä1-1/+4
2022-03-07drm/i915/psr: Set "SF Partial Frame Enable" also on full updateJouni Högander1-2/+14
2022-03-07drm/i915/gmbus: use to_intel_gmbus() instead of open codingJani Nikula1-13/+5
2022-03-07drm/i915/gmbus: move some local bus variables within loopsJani Nikula1-2/+3
2022-03-07drm/i915/fbdev: fixup setting screen_sizeMatthew Auld1-2/+2
2022-03-07drm/i915: Remove the vm open countThomas Hellström1-1/+1
2022-03-04drm/i915: Use bigjoiner_pipes moreVille Syrjälä1-11/+20
2022-03-04drm/i915: Eliminate bigjoiner booleanVille Syrjälä7-45/+37
2022-03-04drm/i915: Start tracking PIPESRC as a drm_rectVille Syrjälä9-78/+96
2022-03-04drm/i915: Use designated initializers for bxt_dp_clk_val[]Ville Syrjälä1-7/+7
2022-03-04drm/i915: Remove bxt m2_frac_enVille Syrjälä1-10/+8
2022-03-04drm/i915: Clean up some struct/array initializersVille Syrjälä1-9/+9
2022-03-04drm/i915: Move a bunch of stuff into rodata from the stackVille Syrjälä1-12/+12
2022-03-04drm/i915: Nuke skl_wrpll_context_init()Ville Syrjälä1-10/+3
2022-03-04drm/i915: Relocate a few more pch transcoder bitsVille Syrjälä5-19/+26
2022-03-04drm/i915: Relocate ibx pch port sanitation codeVille Syrjälä3-62/+71
2022-03-04drm/i915: Remove framestart_delay sanitationVille Syrjälä1-56/+0
2022-03-04drm/i915: Move framestart_delay to crtc_stateVille Syrjälä4-19/+42
2022-03-04drm/i915/dmc: Update DMC to v2.16 on ADL-PMadhumitha Tolakanahalli Pradeep1-2/+2
2022-03-04drm/i915/gmbus: alloc intel_gmbus dynamicallyJani Nikula1-13/+29
2022-03-04drm/i915/gmbus: pass gpio reg to intel_gpio_setup()Jani Nikula1-4/+3
2022-03-04drm/i915/gmbus: reduce gmbus pin lookups in gmbus setupJani Nikula1-3/+5
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