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path: root/drivers/gpu/drm/i915/i915_pci.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2020-02-26drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgttChris Wilson1-2/+2
2019-12-28drm/i915: simplify prefixes on device_infoLucas De Marchi1-115/+115
2019-12-13drm/i915/perf: Register sysctl path globallyVenkata Sandeep Dhanalakota1-1/+8
2019-12-12drm/i915/cml: Separate U series pci id from origianl list.Lee Shawn C1-0/+2
2019-12-03drm/i915/gt: Set the PD again for HaswellChris Wilson1-1/+1
2019-11-30drm/i915/gen7: Re-enable full-ppgtt for ivb & hswChris Wilson1-1/+1
2019-11-11drm/i915/selftests: Perform some basic cycle counting of MI opsChris Wilson1-0/+6
2019-10-29drm/i915/display/cnl+: Handle fused off DSCJosé Roberto de Souza1-0/+1
2019-10-29drm/i915/display: Handle fused off HDCPJosé Roberto de Souza1-0/+2
2019-10-25drm/i915: add new gen12 dgfx platform macroStuart Summers1-0/+4
2019-10-18drm/i915: treat stolen as a regionMatthew Auld1-1/+1
2019-10-18drm/i915: treat shmem as a regionMatthew Auld1-8/+21
2019-10-02drm/i915/display: abstract all vgaarb access to intel_vga.[ch]Jani Nikula1-1/+0
2019-09-24drm/i915/tgl: Swap engines for no rps (gpu reclocking)Chris Wilson1-1/+1
2019-09-24drm/i915: Add Pipe D cursor ctrl register for Gen12Ankit Nautiyal1-0/+9
2019-09-23drm/i915/dsb: Enable DSB for gen12.Animesh Manna1-1/+2
2019-09-17drm/i915/tgl: Extend MI_SEMAPHORE_WAITChris Wilson1-1/+0
2019-09-13drm/i915/tgl: Re-enable rc6Mika Kuoppala1-1/+0
2019-09-13drm/i915/tgl: Limit ourselves to just rcs0Chris Wilson1-0/+1
2019-09-12drm/i915/tgl: Disable preemption while being debuggedChris Wilson1-0/+1
2019-09-12drm/i915: convert device info num_pipes to pipe_maskJani Nikula1-12/+12
2019-09-10drm/i915/tgl: Disable rc6 for debuggingChris Wilson1-0/+1
2019-08-30drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgttChris Wilson1-1/+1
2019-08-30drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgttChris Wilson1-2/+2
2019-08-10drm/i915/gtt: disable 2M pages for pre-gen11Matthew Auld1-4/+7
2019-08-06drm/i915: Use drm_i915_private directly from drv_get_drvdata()Chris Wilson1-7/+7
2019-08-02drm/i915: Add i915 to i915_inject_probe_failureMichal Wajdeczko1-1/+1
2019-07-31drm/i915/tgl: Tigerlake only has global MOCS registersMichel Thierry1-1/+2
2019-07-25drm/i915/uc: Unify uC platform checkDaniele Ceraolo Spurio1-2/+2
2019-07-12drm/i915/tgl: add modular FIA to device infoLucas De Marchi1-0/+1
2019-07-12drm/i915: Replace "_load" with "_probe" consequentlyJanusz Krzysztofik1-1/+1
2019-07-12drm/i915: Rename "_load"/"_unload" to match PCI entry pointsJanusz Krzysztofik1-2/+2
2019-07-11drm/i915/tgl: Add TGL PCI IDsLucas De Marchi1-0/+1
2019-07-11drm/i915/tgl: add initial Tiger Lake definitionsDaniele Ceraolo Spurio1-0/+29
2019-06-25drm/i915/ehl: Add missing VECS engineJosé Roberto de Souza1-1/+1
2019-06-17drm/i915: move modesetting core code under display/Jani Nikula1-1/+2
2019-06-17drm/i915/icl: Add Multi-segmented gamma supportShashank Sharma1-1/+1
2019-06-09drm/i915/guc: always use Command Transport BuffersDaniele Ceraolo Spurio1-1/+0
2019-05-31drm/i915: add force_probe module parameter to replace alpha_supportJani Nikula1-5/+46
2019-05-28drm/i915/guc: Enable GuC CTB communication on Gen11Michal Wajdeczko1-0/+1
2019-05-06drm/i915: Move w/a 0477/WaDisableIPC:skl into intel_init_ipc()Ville Syrjälä1-2/+0
2019-04-19drm/i915: Track HAS_RPS alongside HAS_RC6 in the device infoChris Wilson1-0/+5
2019-04-08drm/i915: extract intel_fbdev.h from intel_drv.hJani Nikula1-0/+1
2019-04-03drm/i915: Expose full 1024 LUT entries on ivb+Ville Syrjälä1-1/+1
2019-04-03drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3Ville Syrjälä1-0/+5
2019-04-03drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä1-0/+6
2019-04-03drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä1-0/+4
2019-04-03drm/i915: Implement split/10bit gamma for ivb/hswVille Syrjälä1-3/+3
2019-04-01drm/i915: Introduce concept of a sub-platformTvrtko Ursulin1-1/+1
2019-04-01drm/i915: Split Pineview device info into desktop and mobileTvrtko Ursulin1-2/+10
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