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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-10-18drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar1-0/+3
2018-09-13drm/i915/skl+: Decode memory bandwidth and parametersMahesh Kumar1-0/+18
2018-09-13drm/i915/bxt: Decode memory bandwidth and parametersMahesh Kumar1-0/+30
2018-09-11drm/i915/icl: Define T_INIT_MASTER registersMadhav Chauhan1-0/+6
2018-09-04drm/i915/icl: Fix context RPCS programmingTvrtko Ursulin1-0/+2
2018-08-28drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engineManasi Navare1-2/+2
2018-08-24drm/i915/icl: implement the tc/legacy HPD {dis,}connect flowsPaulo Zanoni1-0/+6
2018-08-22drm/i915: Rename PLANE_CTL_DECOMPRESSION_ENABLEDhinakaran Pandiyan1-1/+1
2018-08-20drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare1-0/+5
2018-08-20drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value definesManasi Navare1-1/+4
2018-08-16drm/i915: remove confusing GPIO vs PCH_GPIOLucas De Marchi1-19/+5
2018-08-16drm/i915: make PCH_GMBUS* definitions private to gvtLucas De Marchi1-7/+0
2018-08-14drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula1-0/+1
2018-08-08drm/i915/icl: Add missing power gate enumsImre Deak1-0/+2
2018-08-08drm/i915: Use existing power well IDs where possibleImre Deak1-3/+0
2018-08-08drm/i915: Make power well ID names more uniformImre Deak1-5/+5
2018-08-08drm/i915: Remove redundant power well IDsImre Deak1-105/+13
2018-08-08drm/i915/ddi: Use power well CTL IDX instead of IDImre Deak1-44/+84
2018-08-08drm/i915/vlv: Use power well CTL IDX instead of IDImre Deak1-5/+17
2018-08-03drm/i915: Clear all residual RPS events on disabling interruptsChris Wilson1-2/+4
2018-08-01Revert "drm/i915/icl: WaEnableFloatBlendOptimization"Mika Kuoppala1-3/+0
2018-07-27drm/i915/icl: Set TBT IO in Aux transactionAnusha Srivatsa1-0/+1
2018-07-25drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni1-0/+20
2018-07-25drm/i915/icl: program MG_DP_MODEPaulo Zanoni1-0/+15
2018-07-25drm/i915/icl: Update FIA supported lane count for hpd.Animesh Manna1-0/+3
2018-07-25drm/i915/icl: implement icl_digital_port_connected()Paulo Zanoni1-0/+8
2018-07-24drm/i915/icl: Add remaining registers and bitfields for MG PHY DDIManasi Navare1-113/+157
2018-07-20drm/i915/dsc: Add missing _MMIO() from PPS registersAnusha Srivatsa1-38/+38
2018-07-18i915/dp/dsc: Add Rate Control Range Parameter RegistersAnusha Srivatsa1-0/+104
2018-07-18i915/dp/dsc: Add Rate Control Buffer Threshold RegistersAnusha Srivatsa1-0/+51
2018-07-18i915/dp/dsc: Add DSC PPS register definitionsAnusha Srivatsa1-0/+255
2018-07-18drm/i915/icl: Add VIDEO_DIP registersAnusha Srivatsa1-0/+23
2018-07-12drm/i915/gmbus: Enable burst readRamalingam C1-0/+1
2018-07-12drm/i915/gmbus: Increase the Bytes per Rd/Wr OpRamalingam C1-0/+1
2018-07-10drm/i915: use the ICL stolen memoryPaulo Zanoni1-0/+1
2018-07-06drm/i915/icl: Define AUX lane registers for Port A/BMadhav Chauhan1-0/+23
2018-07-06drm/i915/icl: Define PORT_CL_DW_10 registerMadhav Chauhan1-0/+20
2018-07-06drm/i915/icl: Define DSI mode ctl registerMadhav Chauhan1-0/+8
2018-07-06drm/i915/icl: Program DSI Escape clock DividerMadhav Chauhan1-0/+1
2018-07-05drm/i915/icl: Define register for DSI PLLMadhav Chauhan1-0/+15
2018-07-04drm/i915: Fix pre-ILK error interrupt ackVille Syrjälä1-1/+0
2018-07-02drm/i915/psr: Add psr1 live statusVathsala Nagaraju1-0/+1
2018-07-02drm/i915: abstract and document register picking macrosJani Nikula1-6/+22
2018-06-27drm/i915/icp: Add Interrupt SupportAnusha Srivatsa1-1/+40
2018-06-27drm/i915/icl: Add power well supportImre Deak1-9/+69
2018-06-26drm/i915/psr: Enable CRC check in the static frame on the sink sideJosé Roberto de Souza1-0/+1
2018-06-21drm/i915: Enable hw workaround to bypass alphaVandita Kulkarni1-0/+8
2018-06-21drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak1-0/+13
2018-06-18drm/i915/icl: Handle hotplug interrupts for DP over TBTDhinakaran Pandiyan1-1/+10
2018-06-18drm/i915/icl: Support for TC North Display interruptsDhinakaran Pandiyan1-0/+20
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