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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2013-11-29drm/i915: Make the DERRMR SRM target global GTTVille Syrjälä1-0/+1
2013-11-10Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel into drm-nextDave Airlie1-2/+121
2013-11-08drm/i915: Wire up cpu fifo underrun reporting support for bdwDaniel Vetter1-1/+1
2013-11-08drm/i915: Wire up port A aux channelDaniel Vetter1-1/+2
2013-11-08drm/i915: Fix up the bdw pipe interrupt enable listsDaniel Vetter1-5/+4
2013-11-08drm/i915: Optimize pipe irq handling on bdwDaniel Vetter1-4/+1
2013-11-08drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPointsBen Widawsky1-0/+1
2013-11-08drm/i915/bdw: conservative SBE VUE cache modeBen Widawsky1-0/+2
2013-11-08drm/i915/bdw: Limit SDE poly depth FIFO to 2Ben Widawsky1-0/+1
2013-11-08drm/i915/bdw: Sampler power bypass disableBen Widawsky1-0/+1
2013-11-08ddrm/i915/bdw: Disable centroid pixel perf optimizationBen Widawsky1-0/+3
2013-11-08drm/i915/bdw: BWGTLB clock gate disableBen Widawsky1-0/+1
2013-11-08drm/i915/bdw: Implement edp PSR workaroundsBen Widawsky1-0/+6
2013-11-08drm/i915/bdw: Support eDP PSRBen Widawsky1-2/+2
2013-11-08drm/i915/bdw: Use The GT mailbox for IPS enable/disableBen Widawsky1-0/+1
2013-11-08drm/i915/bdw: Add Broadwell display FIFO limitsVille Syrjälä1-0/+1
2013-11-08drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasisPaulo Zanoni1-0/+11
2013-11-08drm/i915/bdw: get the correct LCPLL frequency on BroadwellPaulo Zanoni1-0/+3
2013-11-08drm/i915/bdw: Broadwell has PIPEMISCPaulo Zanoni1-0/+12
2013-11-08drm/i915/bdw: Implement PPGTT enableBen Widawsky1-0/+3
2013-11-08drm/i915/bdw: Support BDW cachingBen Widawsky1-0/+1
2013-11-08drm/i915/bdw: dispatch updates (64b related)Ben Widawsky1-0/+1
2013-11-08drm/i915/bdw: Implement interrupt changesBen Widawsky1-0/+68
2013-11-08drm/i915/bdw: display stuffBen Widawsky1-0/+1
2013-11-08drm/i915/bdw: HW context supportBen Widawsky1-0/+3
2013-11-08drm/i915/bdw: Swizzling supportBen Widawsky1-0/+2
2013-11-06drm/i915/vlv: use per-pipe backlight controls v2Jesse Barnes1-0/+15
2013-11-05drm/i915/vlv: enable HDA display audio for Valleyview2Mengdong Lin1-0/+18
2013-11-04Merge tag 'v3.12' into drm-intel-nextDaniel Vetter1-0/+12
2013-11-01drm/i915: scramble reset support for DP port CRC on g4xDaniel Vetter1-0/+8
2013-10-31drm/i915/vlv: Fix typo in the DPIO register define.Chon Ming Lee1-1/+1
2013-10-30drm/i915: refactor ilk display interrupt handlingDaniel Vetter1-2/+5
2013-10-30drm/i915: Capture batchbuffer state upon GPU hangChris Wilson1-0/+1
2013-10-27drm/i915: Remove WaFbcDisableDpfcClockGating on HSWBen Widawsky1-3/+0
2013-10-27drm/i915: Convert straggling MCHBAR registersBen Widawsky1-4/+4
2013-10-21drm/i915: Wire up gen2 CRC supportDaniel Vetter1-0/+1
2013-10-21drm/i915: Fix PIPE_CRC_CTL for vlvDaniel Vetter1-2/+1
2013-10-21drm/i915: CRC source selection #defines for gmch/vlv chipsDaniel Vetter1-0/+22
2013-10-21drm/i915: Adjust CRC capture for pre-gen5/vlvDaniel Vetter1-15/+15
2013-10-18drm/i915: Disable GGTT PTEs on GEN6+ suspendBen Widawsky1-0/+4
2013-10-18drm/i915: crc support for hswDaniel Vetter1-0/+1
2013-10-18drm/i915: wire up CRC interrupt for ilk/snbDaniel Vetter1-0/+2
2013-10-18drm/i915: add CRC #defines for ilk/snbDaniel Vetter1-11/+35
2013-10-18drm/i915: set HDMI pixel clock in audio configurationJani Nikula1-1/+11
2013-10-16drm/i915: Expose latest 200 CRC value for pipe through debugfsShuang He1-1/+35
2013-10-15drm/i915: Adjust watermark register masksVille Syrjälä1-5/+5
2013-10-15drm/i915: disable LVDS clock gating on CPT v2Jesse Barnes1-0/+2
2013-10-11drm/i915: Fix VLV frame counter registersVille Syrjälä1-8/+8
2013-10-04drm/i915/vlv: Turn off power gate for BIOS-less system.Chon Ming Lee1-0/+9
2013-10-04drm/i915/vlv: reset DPIO on load and resume v2Jesse Barnes1-1/+1
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