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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-02-02drm/i915: Parameterize MI_PREDICATE registersMatt Roper1-10/+1
2022-02-02drm/i915: Parameterize R_PWR_CLK_STATE register definitionMatt Roper1-15/+0
2022-02-02drm/i915/perf: Move OA regs to their own headerMatt Roper1-485/+0
2022-02-02drm/i915: remove VGA register definitionsJani Nikula1-41/+0
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-16/+155
2022-01-31drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for referenceUmesh Nerlige Ramappa1-1/+2
2022-01-28drm/i915/dg2: Add Wa_14015227452Matt Roper1-0/+1
2022-01-28drm/i915: Clean up M/N register definesVille Syrjälä1-19/+3
2022-01-26drm/i915: Clean up PIPESRC definesVille Syrjälä1-0/+4
2022-01-26drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit definesVille Syrjälä1-32/+26
2022-01-26drm/i915: Clean up PIPECONF bit definesVille Syrjälä1-56/+52
2022-01-26drm/i915: Clean up SKL_BOTTOM_COLOR definesVille Syrjälä1-2/+2
2022-01-26drm/i915: Clean up PIPEMISC register definesVille Syrjälä1-16/+19
2022-01-26drm/i915: Bump DSL linemask to 20 bitsVille Syrjälä1-2/+2
2022-01-25drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for referenceUmesh Nerlige Ramappa1-1/+2
2022-01-25drm/i915: Flush TLBs before releasing backing storeTvrtko Ursulin1-0/+11
2022-01-24drm/i915/dg2: Add Wa_18018781329Matt Roper1-0/+4
2022-01-24drm/i915: Clean up pre-skl primary plane registersVille Syrjälä1-46/+62
2022-01-20drm/i915: Clean up vlv/chv sprite plane registersVille Syrjälä1-38/+65
2022-01-18drm/i915: Clean up cursor registersVille Syrjälä1-32/+39
2022-01-18drm/i915: Clean up g4x+ sprite plane registersVille Syrjälä1-28/+45
2022-01-18drm/i915: Clean up ivb+ sprite plane registersVille Syrjälä1-32/+49
2022-01-18drm/i915: Use REG_BIT() & co. for universal plane bitsVille Syrjälä1-87/+110
2022-01-18drm/i915: Sipmplify PLANE_STRIDE maskingVille Syrjälä1-2/+1
2022-01-17drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza1-2/+6
2022-01-13drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza1-2/+6
2022-01-11drm/i915: Move TC PHY registers to their own headerMatt Roper1-333/+0
2022-01-11drm/i915: Move combo PHY registers to their own headerMatt Roper1-154/+0
2022-01-11drm/i915: Move SNPS PHY registers to their own headerMatt Roper1-67/+0
2022-01-11drm/i915/gt: Move engine registers to their own headerMatt Roper1-174/+2
2022-01-11drm/i915: Introduce i915_reg_defs.hMatt Roper1-87/+1
2022-01-11drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7Matt Roper1-1/+0
2022-01-11drm/i915: Use RING_PSMI_CTL rather than per-engine macrosMatt Roper1-12/+7
2022-01-11drm/i915: Parameterize ECOSKPDMatt Roper1-8/+6
2022-01-11drm/i915: Parameterize PWRCTX_MAXCNTMatt Roper1-5/+1
2022-01-11drm/i915: Use parameterized GPR register definitions everywhereMatt Roper1-8/+0
2022-01-10drm/i915: split out vlv sideband registers from i915_reg.hJani Nikula1-171/+0
2022-01-10drm/i915: split out PCI config space registers from i915_reg.hJani Nikula1-78/+0
2021-12-24Merge tag 'drm-intel-gt-next-2021-12-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-0/+4
2021-12-21drm/i915/guc: Request RP0 before loading firmwareVinay Belgaumkar1-0/+4
2021-12-17Merge tag 'drm-intel-next-2021-12-14' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-nextDave Airlie1-19/+29
2021-12-16drm/i915/dg1: Read OPROM via SPI controllerClint Taylor1-0/+8
2021-12-15drm/i915/fbc: Parametrize FBC register offsetsVille Syrjälä1-17/+17
2021-12-10Merge tag 'drm-intel-gt-next-2021-12-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-16/+140
2021-12-07drm/i915/display/dg2: Set CD clock squashing registersMika Kahola1-0/+8
2021-12-07drm/i915/snps: use div32 version of MPLLB word clock for UHBRJani Nikula1-0/+1
2021-12-03drm/i915: Rename PLANE_CUS_CTL Y plane bitsVille Syrjälä1-4/+4
2021-12-03drm/i915: Rename plane YUV order bitsVille Syrjälä1-7/+7
2021-12-03drm/i915: Get rid of the 64bit PLANE_CC_VAL mmioVille Syrjälä1-6/+6
2021-12-02drm/i915/dg2: Add Wa_14010547955Matt Roper1-2/+3
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