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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
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2015-05-08Merge tag 'drm-intel-next-2015-04-23-fixed' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie1-32/+457
2015-04-28drm/i915/chv: Implement WaDisableShadowRegForCpdDeepak S1-0/+2
2015-04-23drm/i915: cope with large i2c transfersDmitry Torokhov1-0/+1
2015-04-16drm/i915/bxt: VSwing programming sequenceVandana Kannan1-0/+61
2015-04-16drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M1-0/+76
2015-04-16drm/i915/bxt: Implement enable/disable for Display C9 stateA.Sunil Kamath1-0/+5
2015-04-16drm/i915/bxt: add description about the BXT PHYsImre Deak1-6/+12
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan1-0/+96
2015-04-16drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan1-0/+20
2015-04-14drm/i915: PSR: Remove wrong LINK_DISABLE.Rodrigo Vivi1-1/+0
2015-04-14drm/i915/bxt: Enable GMBUS IRQShashank Sharma1-0/+1
2015-04-14drm/i915/bxt: DDI Hotplug interrupt setupShashank Sharma1-1/+22
2015-04-14drm/i915: add bxt gmbus supportJani Nikula1-0/+3
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter1-12/+14
2015-04-14drm/i915/bxt: add workaround to avoid PTE corruptionRobert Beckett1-0/+1
2015-04-14drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaroundBen Widawsky1-0/+4
2015-04-14drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaroundBen Widawsky1-0/+1
2015-04-13drm/i915: Register definitions for skylake scalersChandra Konduru1-0/+115
2015-04-10drm/i915/skl: Support for 90/270 rotationSonika Jindal1-0/+2
2015-04-10drm/i915: Naming constants to be written to GEN9_PG_ENABLESagar Kamble1-0/+2
2015-04-10drm/i915: Agressive downclocking on BaytrailChris Wilson1-2/+0
2015-04-10drm/i915/skl: Implement WaDisableVFUnitClockGatingDamien Lespiau1-0/+1
2015-04-09drm/i915/bxt: Support BXT in SSEU device status dumpJeff McGee1-9/+4
2015-04-09drm/i915/bxt: Determine BXT slice/subslice/EU infoJeff McGee1-3/+1
2015-04-09drm/i915/bxt: Add the plane4 related interrupt definitionsDamien Lespiau1-0/+3
2015-04-07drm/i915/bdw: WaProgramL3SqcReg1DefaultRodrigo Vivi1-0/+3
2015-04-07drm/i915/skl: Enabling PSR2 SU with frame syncSonika Jindal1-0/+14
2015-04-01drm/i915: index gmbus tables using the pin pair numberJani Nikula1-1/+1
2015-04-01drm/i915: rename GMBUS_PORT_* macros as GMBUS_PIN_*Jani Nikula1-10/+10
2015-03-25drm/i915: Add fault address to error state for gen8 and gen9Mika Kuoppala1-0/+3
2015-03-20drm/i915: Use down ei for manual Baytrail RPS calculationsChris Wilson1-1/+0
2015-03-20drm/i915: Improved w/a for rps on BaytrailChris Wilson1-2/+2
2015-03-17drm/i915/skl: Added new macrosAkash Goel1-0/+9
2015-03-17drm/i915: Use FW_WM() macro for older gmch platforms tooVille Syrjälä1-2/+2
2015-03-17drm/i915: Add polish to VLV WM shift+mask operationsVille Syrjälä1-5/+5
2015-03-17drm/i915: Disable DDR DVFS on CHVVille Syrjälä1-0/+5
2015-03-17drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä1-0/+3
2015-03-17drm/i915: Program PFI credits for VLVVidya Srinivas1-0/+8
2015-03-17drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä1-2/+2
2015-03-17drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman1-0/+2
2015-03-17drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman1-0/+1
2015-03-17drm/i915: Disable M2 frac division for integer caseVijay Purushothaman1-0/+1
2015-03-17drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee1-0/+11
2015-03-17drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee1-0/+2
2015-03-17drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä1-0/+3
2015-03-17drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä1-1/+4
2015-03-17drm/i915: Hide VLV DDL precision handlingVille Syrjälä1-6/+2
2015-03-17drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä1-4/+0
2015-03-17drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä1-0/+1
2015-03-17drm/i915: Fix trivial typos in comments and warning messageYannick Guerrini1-1/+1
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