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path: root/drivers/gpu/drm/i915/intel_dsi_pll.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-07-06drm/i915/dsi: rename the current DSI files based on first platformJani Nikula1-650/+0
2017-02-28drm/i915/glk: Validate only DSI PORT A PLL dividerMadhav Chauhan1-6/+13
2017-02-28drm/i915/glk: Program txesc clock divider for GLKDeepak M1-2/+59
2017-02-28drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXTDeepak M1-10/+15
2017-02-28drm/i915/glk: Add DSI PLL divider range for glkDeepak M1-7/+17
2017-02-15drm/i915: Fix PLL 8x/3 divider for MIPI video modeUma Shankar1-5/+1
2016-12-16drm/i915: relax uncritical udelay_range()Nicholas Mc Guire1-2/+4
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira1-6/+6
2016-10-14drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin1-13/+13
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson1-6/+6
2016-07-02drm/i915: Fix buffer overflow in dsi_calc_mnp()Chris Wilson1-8/+9
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-1/+5
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-2/+5
2016-04-15drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()Ville Syrjälä1-22/+6
2016-04-15drm/i915: Compute DSI PLL parameters during .compute_config()Ville Syrjälä1-70/+86
2016-04-12drm/i915: Fix CHV DSI PLL refclk during state readoutVille Syrjälä1-1/+1
2016-04-12drm/i915: Power down the DSI PLL before reconfiguring itVille Syrjälä1-8/+0
2016-04-12drm/i915: Change lfsr_converts[] to u16Ville Syrjälä1-1/+1
2016-03-24drm/i915/bxt: Fix DSI HW state readoutImre Deak1-0/+40
2016-03-16drm/i915/dsi: start using enum mipi_dsi_pixel_formatJani Nikula1-25/+5
2016-03-16drm/i915/dsi: lose the loose 666 format name in favor of packedJani Nikula1-2/+2
2016-03-03drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwardsDeepak M1-17/+39
2016-02-19drm/i915/dsi: Using the bpp value wrt the pixel formatDeepak M1-1/+1
2016-01-08drm/i915/dsi: remove unused dsi_rr_formula()Jani Nikula1-81/+0
2016-01-08drm/i915/dsi: abstract get pclk platform differencesJani Nikula1-2/+10
2015-12-10drm/i915: Separate cherryview from valleyviewWayne Boyer1-3/+3
2015-10-06drm/i915/bxt: vlv_dsi_reset_clocks() can be statickbuild test robot1-2/+2
2015-10-02drm/i915/bxt: get DSI pixelclockShashank Sharma1-0/+35
2015-10-02drm/i915/bxt: DSI disable and post-disableShashank Sharma1-0/+39
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma1-0/+42
2015-09-23drm/i915/bxt: Disable DSI PLL for BXTShashank Sharma1-1/+31
2015-09-23drm/i915/bxt: Enable BXT DSI PLLShashank Sharma1-1/+94
2015-07-03drm/i915: Changes required to enable DSI Video Mode on CHTGaurav K Singh1-6/+20
2015-07-03drm/i915: Support for higher DSI clkGaurav K Singh1-2/+2
2015-07-03drm/i915/dsi: abstract dsi bpp derivation from pixel formatJani Nikula1-43/+24
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä1-7/+7
2015-05-20drm/i915/dsi: add support for DSI PLL N1 divisor valuesJani Nikula1-6/+11
2015-05-20drm/i915: clean up dsi pll calculationJani Nikula1-36/+17
2014-12-10drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port CGaurav K Singh1-2/+3
2014-12-05drm/i915: cck reg used for checking DSI Pll lockedGaurav K Singh1-2/+4
2014-12-05drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual linkGaurav K Singh1-0/+3
2014-08-08drm/i915: Align intel_dsi*.c files a bitDaniel Vetter1-4/+4
2014-08-08drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar1-6/+3
2014-08-07drm/i915: Add correct hw/sw config check for DSI encoderShobhit Kumar1-0/+81
2013-12-11drm/i915: Try harder to get best m, n, p values with minimal errorShobhit Kumar1-10/+20
2013-12-11drm/i915: Compute dsi_clk from pixel clockShobhit Kumar1-58/+31
2013-09-16drm/i915: Use adjusted_mode in DSI PLL calculationsVille Syrjälä1-2/+2
2013-09-04drm/i915: add VLV DSI PLL Calculationsymohanma1-0/+317
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