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path: root/drivers/gpu/drm/i915/intel_pm.c (follow)
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2014-07-06Merge tag 'drm-intel-fixes-2014-07-03' of git://anongit.freedesktop.org/drm-intelDave Airlie1-0/+8
2014-07-04Merge tag 'sound-3.16-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/soundLinus Torvalds1-0/+21
2014-07-04drm/i915: provide interface for audio driver to query cdclkJani Nikula1-0/+21
2014-07-01drm/i915: Drop early VLV WA to fix Voltage not getting dropped to VminDeepak S1-0/+8
2014-06-23drm/i915: cache hw power well enabled stateImre Deak1-22/+15
2014-06-19Merge tag 'sound-3.16-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/soundLinus Torvalds1-6/+8
2014-06-16drm/i915, HD-audio: Don't continue probing when nomodeset is givenTakashi Iwai1-6/+8
2014-06-13drm/i915/bdw: remove erroneous chv specific workarounds from bdw codeTom O'Rourke1-5/+1
2014-06-11drm/i915: Disable FBC by default also on Haswell and laterChris Wilson1-2/+1
2014-06-06Merge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie1-12/+83
2014-06-05Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-nextDave Airlie1-0/+40
2014-06-05drm/i915: fix display power sw state reportingImre Deak1-1/+16
2014-06-05drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMSVille Syrjälä1-0/+3
2014-06-05drm/i915: Enable interrupt-based AGPBUSY# enable on 85xVille Syrjälä1-0/+4
2014-06-05drm/i915: Flip the sense of AGPBUSY_DIS bitVille Syrjälä1-1/+1
2014-06-05drm/i915: Set AGPBUSY# bit in init_clock_gatingVille Syrjälä1-0/+3
2014-06-05drm/i915/vlv: add pll assertion when disabling DPIO common wellJesse Barnes1-0/+4
2014-06-05drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_wellJesse Barnes1-9/+30
2014-06-05drm/i915/vlv: re-order power wells so DPIO common comes after TXJesse Barnes1-6/+6
2014-06-05drm/i915/vlv: move CRI refclk enable into __vlv_set_power_wellJesse Barnes1-0/+11
2014-06-05drm/i915/vlv: assert and de-assert sideband reset at boot and resume v3Jesse Barnes1-3/+10
2014-06-05drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlvAkash Goel1-2/+5
2014-05-22drm/i915: s/intel_ring_buffer/intel_engine_csOscar Mateo1-5/+5
2014-05-22drm/i915: fix possible RPM ref leaking during RPS disablingImre Deak1-1/+3
2014-05-21Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queuedDaniel Vetter1-40/+0
2014-05-21drm/i915: Accurately initialize fifo underrun state on gmch platformsDaniel Vetter1-6/+0
2014-05-21drm/i915: rip our vblank reset hacks for runtime PMDaniel Vetter1-34/+0
2014-05-20drm/i915/chv: Add a bunch of pre production workaroundsVille Syrjälä1-1/+19
2014-05-20drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHVRafael Barbalho1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableSDEUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableCSUnitClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCountFullforceMissDisable:chvVille Syrjälä1-0/+6
2014-05-20drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chvVille Syrjälä1-0/+4
2014-05-20drm/i915/chv: Implement WaDisablePartialInstShootdown:chvVille Syrjälä1-0/+4
2014-05-16drm/i915: Be careful with non-disp bit in PMINTRMSKMika Kuoppala1-1/+1
2014-05-15drm/i915: Enable rc6 with bdwMika Kuoppala1-6/+2
2014-05-15drm/i915: Fix rc6 options debug infoMika Kuoppala1-1/+1
2014-05-15drm/i915: Enable PM Interrupts target via Display Interface.Deepak S1-0/+3
2014-05-15drm/i915/bdw: Implement a basic PM interrupt handlerBen Widawsky1-2/+36
2014-05-15drm/i915: Increase WM memory latency values on SNBVille Syrjälä1-0/+40
2014-05-14drm/i915: Use for_each_crtc() when iterating through the CRTCsDamien Lespiau1-3/+3
2014-05-14drm/i915: Use for_each_intel_crtc() when iterating through intel_crtcsDamien Lespiau1-3/+3
2014-05-13drm/i915: Use ilk_wm_max_level() in latency debugfs filesDamien Lespiau1-1/+1
2014-05-12drm/i915/chv: Initial clock gating support for CherryviewVille Syrjälä1-0/+13
2014-05-06drm/i915: Merge LP1+ watermarks in safer wayVille Syrjälä1-9/+28
2014-05-06drm/i915: Make sure computed watermarks never overflow the registersVille Syrjälä1-7/+36
2014-05-05drm/i915: vlv: init only needed state during early power well enablingImre Deak1-4/+10
2014-05-05drm/i915/bdw: Disable idle DOP clock gatingBen Widawsky1-0/+4
2014-05-05drm/i915: bdw: fix RC6 enabled status reporting and disable runtime PMImre Deak1-0/+4
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