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path: root/drivers/gpu/drm/i915/intel_pm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2013-12-13drm/i915: get a PC8 reference when enabling the power wellPaulo Zanoni1-2/+12
2013-12-12Merge tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixesDave Airlie1-1/+10
2013-12-12Merge branch 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixesDave Airlie1-1/+17
2013-12-06drm/i915: fix pm init orderingDaniel Vetter1-1/+10
2013-11-27drm/i915: use crtc_htotal in watermark calculations to match fastboot v2Jesse Barnes1-7/+8
2013-11-20drm/i915: Fix gen3 self-refresh watermarksDaniel Vetter1-1/+1
2013-11-16Partially revert "drm/i915: tune the RC6 threshold for stability"Daniel Vetter1-1/+1
2013-11-14drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwellBen Widawsky1-1/+17
2013-11-08drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPointsBen Widawsky1-0/+3
2013-11-08drm/i915/bdw: conservative SBE VUE cache modeBen Widawsky1-0/+3
2013-11-08drm/i915/bdw: Limit SDE poly depth FIFO to 2Ben Widawsky1-0/+3
2013-11-08drm/i915/bdw: Sampler power bypass disableBen Widawsky1-0/+2
2013-11-08ddrm/i915/bdw: Disable centroid pixel perf optimizationBen Widawsky1-0/+4
2013-11-08drm/i915/bdw: BWGTLB clock gate disableBen Widawsky1-0/+2
2013-11-08drm/i915/bdw: Implement edp PSR workaroundsBen Widawsky1-0/+12
2013-11-08drm/i915/bdw: Create a separate BDW rps enableBen Widawsky1-0/+75
2013-11-08drm/i915/bdw: Use HSW formula for ring freq scalingBen Widawsky1-1/+4
2013-11-08drm/i915/bdw: Add Broadwell display FIFO limitsVille Syrjälä1-9/+24
2013-11-08drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriorityBen Widawsky1-0/+6
2013-11-08drm/i915/bdw: Broadwell also has the "power down well"Paulo Zanoni1-2/+3
2013-11-08drm/i915/bdw: Clock gating initBen Widawsky1-0/+11
2013-11-04Merge tag 'v3.12' into drm-intel-nextDaniel Vetter1-1/+8
2013-10-31drm/i915: add back checking for i915_disable_power_wellImre Deak1-1/+1
2013-10-29drm/i915: rename i915_init_power_well to init_power_domains_initImre Deak1-5/+5
2013-10-27drm/i915: remove device field from struct power_wellImre Deak1-9/+20
2013-10-27drm/i915: use power get/put instead of set for power on after initImre Deak1-36/+1
2013-10-27drm/i915: prepare for multiple power wellsImre Deak1-21/+34
2013-10-27drm/i915: Remove WaFbcDisableDpfcClockGating on HSWBen Widawsky1-10/+0
2013-10-27drm/i915: Remove WaFbcDisableDpfcClockGating on IVBBen Widawsky1-10/+0
2013-10-27drm/i915: Convert straggling MCHBAR registersBen Widawsky1-1/+1
2013-10-21drm/i915: change power_well->lock to be mutexImre Deak1-13/+13
2013-10-21drm/i915: factor out is_always_on_domainImre Deak1-54/+30
2013-10-21drm/i915: Print RC6 info less oftenBen Widawsky1-11/+43
2013-10-15drm/i915: Check 5/6 DDB split only when sprites are enabledVille Syrjälä1-1/+2
2013-10-15drm/i915: Rename ilk_check_wm to ilk_validate_wm_levelVille Syrjälä1-5/+5
2013-10-15drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximumsVille Syrjälä1-8/+8
2013-10-15drm/i915: Remove a somewhat silly debug print from watermark codeVille Syrjälä1-2/+0
2013-10-15drm/i915: Init HSW watermark tracking in intel_modeset_setup_hw_state()Ville Syrjälä1-26/+76
2013-10-15drm/i915: Improve watermark dirtyness checksVille Syrjälä1-18/+80
2013-10-15drm/i915: Store current watermark state in dev_priv->wmVille Syrjälä1-31/+15
2013-10-15drm/i915: Kill fbc_wm_enabled from intel_wm_configVille Syrjälä1-1/+0
2013-10-15drm/i915: Refactor wm_lp to level calculationVille Syrjälä1-1/+7
2013-10-15drm/i915: Check 5/6 DDB split only when sprites are enabledVille Syrjälä1-1/+1
2013-10-15drm/i915: Move some computations out from hsw_compute_wm_parameters()Ville Syrjälä1-19/+14
2013-10-15drm/i915: Use intel_pipe_wm in hsw_find_best_resultsVille Syrjälä1-21/+21
2013-10-15drm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results()Ville Syrjälä1-9/+10
2013-10-15drm/i915: Don't re-compute pipe watermarks except for the affected pipeVille Syrjälä1-39/+28
2013-10-15drm/i915: Add intel_pipe_wm and prepare for watermark pre-computeVille Syrjälä1-76/+116
2013-10-15drm/i915: disable LVDS clock gating on CPT v2Jesse Barnes1-1/+3
2013-10-10drm/i915: Avoid tweaking RPS before it is enabledChris Wilson1-10/+16
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