aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_pm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-09-29drm/i915: split watermark vfuncs from display vtable.Dave Airlie1-20/+20
2021-09-29drm/i915: split clock gating init from display vtableDave Airlie1-24/+24
2021-09-29drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)Dave Airlie1-39/+0
2021-09-29drm/i915: make update_wm take a dev_priv.Dave Airlie1-13/+7
2021-09-29drm/i915/pm: drop get_fifo_size vfunc.Dave Airlie1-9/+11
2021-09-23drm/i915: Fix HPLL watermark readout for g4xVille Syrjälä1-2/+5
2021-09-22drm/i915: Apply WaUse32BppForSRWM to elk as well as ctgVille Syrjälä1-8/+4
2021-09-22drm/i915: Fix g4x cxsr enable conditionVille Syrjälä1-3/+2
2021-09-22drm/i915: Use u8 consistently for active_planes bitmaskVille Syrjälä1-3/+3
2021-08-25drm/i915/dg2: Memory latency values from pcode must be doubledMatt Roper1-14/+15
2021-08-12Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-42/+121
2021-08-12Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-nextDave Airlie1-14/+8
2021-07-30drm/i915: remove explicit CNL handling from intel_pm.cLucas De Marchi1-40/+1
2021-07-22drm/i915/dg2: Add dbuf programmingMatt Roper1-1/+119
2021-07-21drm/i915: Make display workaround upper bounds exclusiveMatt Roper1-1/+1
2021-07-21drm/i915: Make GT workaround upper bounds exclusiveMatt Roper1-3/+3
2021-07-21drm/i915: Program DFR enable/disable as a GT workaroundMatt Roper1-8/+0
2021-07-14Merge branch 'topic/revid_steppings' into drm-intel-nextMatt Roper1-1/+1
2021-07-14Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper1-1/+1
2021-07-14drm/i915/dg1: Use revid->stepping tablesMatt Roper1-1/+1
2021-07-13drm/i915: Settle on "adl-x" in WA commentsJosé Roberto de Souza1-2/+2
2021-06-25drm/i915/display: use max_level to control loopLucas De Marchi1-5/+4
2021-06-25drm/i915/display: fix level 0 adjustement on display ver >= 12Lucas De Marchi1-6/+7
2021-06-24drm/i915: Clean up pre-skl wm calling conventionVille Syrjälä1-47/+52
2021-06-15drm/i915/adl_p: Add initial ADL_P WorkaroundsClint Taylor1-3/+5
2021-06-09drm/i915/adl_p: Same slices mask is not same Dbuf stateStanislav Lisovskiy1-2/+4
2021-06-07drm/i915: replace IS_GEN and friends with GRAPHICS_VERLucas De Marchi1-7/+7
2021-06-04drm/i915: Initialize the mbus_offset to fix Klockwork issueManasi Navare1-1/+1
2021-05-19drm/i915/adl_p: MBUS programmingVandita Kulkarni1-8/+84
2021-05-19drm/i915: Introduce MBUS relative dbuf offsetsVille Syrjälä1-6/+34
2021-05-19drm/i915/adl_p: Add ddb allocation supportVandita Kulkarni1-1/+120
2021-05-19drm/i915/adl_p: Add dedicated SAGV watermarksMatt Roper1-4/+50
2021-05-17Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-1/+1
2021-05-14drm/i915/adl_p: Implement Wa_22011091694José Roberto de Souza1-1/+11
2021-05-14drm/i915/xelpd: Increase maximum watermark lines to 255Matt Roper1-4/+11
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-04-28Merge tag 'drm-next-2021-04-28' of git://anongit.freedesktop.org/drm/drmLinus Torvalds1-240/+302
2021-04-27Fix misc new gcc warningsLinus Torvalds1-1/+1
2021-04-21drm/i915: Polish for_each_dbuf_slice()Ville Syrjälä1-22/+12
2021-04-21drm/i915: Use intel_dbuf_slice_size()Ville Syrjälä1-6/+3
2021-04-21drm/i915: Store dbuf slice mask in device infoVille Syrjälä1-4/+9
2021-04-21drm/i915: Handle dbuf bypass path allocation earlierVille Syrjälä1-8/+1
2021-04-21drm/i915: Collect dbuf device info into a sub-structVille Syrjälä1-7/+7
2021-04-20drm/i915/pm: Make the wm parameter of print_wm_latency a pointerJason Ekstrand1-1/+1
2021-04-19Merge tag 'topic/intel-gen-to-ver-2021-04-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-nextRodrigo Vivi1-24/+24
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi1-24/+24
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper1-4/+4
2021-04-12drm/i915/display: Implement Wa_14013723622José Roberto de Souza1-0/+5
2021-04-12drm/i915: Don't zero out the Y plane's watermarksVille Syrjälä1-2/+2
2021-04-09drm/i915: Don't zero out the Y plane's watermarksVille Syrjälä1-2/+2
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.