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path: root/drivers/gpu/drm/i915/intel_pm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-09-26drm/i915: Move IPC WA #1141 to init_ipc()José Roberto de Souza1-6/+6
2018-09-26drm/i915: Move SKL IPC WA to HAS_IPC()José Roberto de Souza1-4/+0
2018-09-26drm/i915: Do not modifiy reserved bit in gens that do not have IPCJosé Roberto de Souza1-1/+3
2018-09-13drm/i915/kbl+: Enable IPC only for symmetric memory configurationsMahesh Kumar1-0/+5
2018-09-13drm/i915/skl+: don't trust IPC value set by BIOSMahesh Kumar1-3/+1
2018-09-13drm/i915: Implement 16GB dimm wa for latency level-0Mahesh Kumar1-0/+10
2018-08-14drm/i915: Disable runtime-pm using lowlevel functions if !HAS_RC6Chris Wilson1-2/+3
2018-08-13drm/i915: Restrict gen6_reset_rps_interrupts to gen6+Chris Wilson1-1/+1
2018-08-07drm/i915/skl: distribute DDB based on panel resolutionMahesh Kumar1-15/+40
2018-08-07drm/i915: ddb_size is of u16 typeMahesh Kumar1-6/+6
2018-08-02drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG registerPaulo Zanoni1-1/+7
2018-08-02drm/i915: Drop stray clearing of rps->last_adjChris Wilson1-1/+0
2018-07-31drm/i915: Interactive RPS modeChris Wilson1-34/+67
2018-07-30drm/i915: Downgrade Gen9 Plane WM latency errorChris Wilson1-2/+2
2018-07-27drm/i915: inline skl_copy_ddb_for_pipe() to its only callerPaulo Zanoni1-12/+4
2018-07-12drm/i915: Silence warning for no vlv powercontextChris Wilson1-4/+4
2018-06-04drm/i915/icl: Don't update enabled dbuf slices struct until updated in hwMahesh Kumar1-1/+0
2018-05-11drm/i915/icl: Enable Sampler DFROscar Mateo1-1/+8
2018-05-11drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo1-1/+3
2018-04-27drm/i915/icl: update ddb entry start/end mask during hw ddb readoutMahesh Kumar1-7/+19
2018-04-27drm/i915/icl: Enable 2nd DBuf slice only when neededMahesh Kumar1-11/+46
2018-04-27drm/i915/icl: track dbuf slice-2 statusMahesh Kumar1-0/+20
2018-04-09drm/i915: Change use get_new_plane_state instead of existing plane stateMaarten Lankhorst1-2/+0
2018-04-09drm/i915/skl: split skl_compute_ddb functionMahesh Kumar1-69/+88
2018-04-09drm/i915/skl+: nv12 workaround disable WM level 1-7Mahesh Kumar1-0/+11
2018-04-09drm/i915/skl+: make sure higher latency level has higher wm valueMahesh Kumar1-0/+18
2018-04-09drm/i915/skl+: pass skl_wm_level struct to wm compute funcMahesh Kumar1-11/+7
2018-04-09drm/i915/skl+: NV12 related changes for WMMahesh Kumar1-8/+42
2018-04-09drm/i915/skl+: support verification of DDB HW state for NV12Mahesh Kumar1-10/+41
2018-04-09drm/i915/skl+: refactor WM calculation for NV12Mahesh Kumar1-59/+62
2018-04-09drm/i915/skl+: rename skl_wm_values struct to skl_ddb_valuesMahesh Kumar1-8/+8
2018-04-06drm/i915/icl: Enable RC6 and RPS in Gen11Oscar Mateo1-6/+4
2018-04-06drm/i915/icl: Handle RPS interrupts correctly for Gen11Oscar Mateo1-3/+3
2018-03-23drm/i915: Avoid setting ring freq on invalid rps freqsMika Kuoppala1-3/+6
2018-03-08drm/i915: Index the ring frequency table by HW frequency rangeChris Wilson1-5/+4
2018-03-07drm/i915/cnl: Add Wa_2201832410Rodrigo Vivi1-0/+5
2018-03-06drm/i915/cnp: Document WaSouthDisplayDisablePWMCGEGatingRodrigo Vivi1-1/+1
2018-03-06drm/i915/cnl: document WaVFUnitClockGatingDisableRodrigo Vivi1-0/+1
2018-03-01drm/i915/icl: Interrupt handlingMika Kuoppala1-1/+6
2018-02-27drm/i915/cnl: Add WaRsDisableCoarsePowerGatingRodrigo Vivi1-1/+1
2018-02-21drm/i915: Rename drm_i915_gem_request to i915_requestChris Wilson1-2/+2
2018-02-20drm/i915: Drop WaDoubleCursorLP3Latency:ivbVille Syrjälä1-4/+0
2018-02-19drm/i915/: Initialise trans_min for skl_compute_transition_wm()Chris Wilson1-0/+1
2018-02-14drm/i915: Fixup kerneldoc for intel_pm.cChris Wilson1-0/+2
2018-02-13drm/i915: Handle RC6 counter wrapTvrtko Ursulin1-10/+54
2018-02-09drm/i915: Replace some negative Gen checksTvrtko Ursulin1-3/+3
2018-02-09drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin1-4/+4
2018-02-08drm/i915: Remove superfluous worker wakeups when RPS is already boostedChris Wilson1-3/+6
2018-02-07drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm, v2.Maarten Lankhorst1-2/+4
2018-02-01drm/i915/bxt, glk: Avoid long atomic poll during CDCLK changeImre Deak1-2/+4
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