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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-08-15drm/i915/hsw+: Add support for multiple power well regsImre Deak1-17/+20
2017-08-15drm/i915: Work around GCC anonymous union initialization bugImre Deak1-24/+54
2017-08-08drm/i915/cnl: Removing missing DDI_E bits from CNL.Rodrigo Vivi1-2/+0
2017-07-27drm/i915: cleanup the CHICKEN_MISC_2 (re)definitionsPaulo Zanoni1-2/+2
2017-07-27drm/i915: Gather all the power well->domain mappings to one placeImre Deak1-204/+204
2017-07-27drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpersImre Deak1-14/+14
2017-07-27drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpersImre Deak1-188/+43
2017-07-27drm/i915/hsw+: Add has_fuses power well attributeImre Deak1-7/+34
2017-07-27drm/i915/hsw, bdw: Wait for the power well disabled stateImre Deak1-17/+11
2017-07-27drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributesImre Deak1-13/+21
2017-07-27drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macrosImre Deak1-22/+36
2017-07-27drm/i915/hsw, bdw: Split power well set to enable/disable helpersImre Deak1-33/+17
2017-07-27drm/i915/hsw, bdw: Remove redundant state check during power well togglingImre Deak1-23/+13
2017-07-27drm/i915/gen9+: Remove redundant state check during power well togglingImre Deak1-16/+9
2017-07-27drm/i915/gen9+: Remove redundant power well state assert during enablingImre Deak1-6/+1
2017-07-27drm/i915/bxt, glk: Give a proper name to the power well struct phy fieldImre Deak1-11/+11
2017-07-27drm/i915: Check for duplicated power well IDsImre Deak1-0/+18
2017-07-27drm/i915/hsw, bdw: Add an ID for the global display power wellImre Deak1-0/+2
2017-07-27drm/i915/gen2: Add an ID for the display pipes power wellImre Deak1-0/+1
2017-07-27drm/i915: Assign everywhere the always-on power well IDImre Deak1-0/+8
2017-07-27drm/i915: Unify power well ID enumsImre Deak1-13/+16
2017-07-27drm/i915/chv: Add unique power well ID for the pipe A power wellImre Deak1-5/+5
2017-07-10drm/i915/cnl: Add max allowed Cannonlake DC.Rodrigo Vivi1-1/+1
2017-07-06drm/i915/cnl: Fix comment about AUX IO power well enable/disableImre Deak1-2/+9
2017-07-06drm/i915/gen9+: Don't remove secondary power well requestsImre Deak1-46/+63
2017-07-06drm/i915/bxt, glk: Fix assert on conditions for DC9 enablingImre Deak1-1/+3
2017-07-06drm/i915/skl: Don't disable misc IO power well during display uninitImre Deak1-3/+4
2017-07-06drm/i915/gen9+: Add 10 us delay after power well 1/AUX IO pw disablingImre Deak1-0/+6
2017-06-15drm/i915: Add i830 "pipes power well"Ville Syrjälä1-0/+64
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä1-2/+111
2017-06-07drm/i915/cnl: Also need power well sanitize.Rodrigo Vivi1-2/+1
2017-06-07drm/i915/cnl: Add power wells for CNLVille Syrjälä1-4/+132
2017-03-28drm/i915: WARN if the core runtime PM get helpers failImre Deak1-3/+9
2017-02-27drm/i915: Only enable DDI IO power domains after enabling DPLLAnder Conselvan de Oliveira1-29/+39
2017-02-27drm/i915/glk: Don't enable DDI IO power domains during initAnder Conselvan de Oliveira1-6/+3
2017-02-20drm/i915: Add power well SW/HW state verificationImre Deak1-1/+84
2017-02-20drm/i915: Preserve the state of power wells not explicitly enabledImre Deak1-6/+12
2017-02-20drm/i915/gen9: Fix clearing of the BIOS power well request registerImre Deak1-1/+6
2017-02-20drm/i915: Call the sync_hw hook for power wells without a domainImre Deak1-24/+4
2017-02-20drm/i915: Remove redundant toggling from the power well sync_hw hooksImre Deak1-42/+10
2017-02-10drm/i915: Make power domain masks 64 bit longAnder Conselvan de Oliveira1-189/+189
2017-02-08drm/i915: Start moving the cdclk stuff into a distinct state structureVille Syrjälä1-1/+4
2017-02-08drm/i915: s/get_display_clock_speed/get_cdclk/Ville Syrjälä1-2/+1
2017-02-08drm/i915: Avoid BIT(max) - 1 and use GENMASK(max - 1, 0)Joonas Lahtinen1-1/+1
2017-01-24drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.Rodrigo Vivi1-5/+5
2016-12-05drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gatingHans de Goede1-1/+12
2016-12-02drm/i915/glk: Implement core display init/uninit sequence for geminilakeAnder Conselvan de Oliveira1-2/+2
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira1-0/+39
2016-12-02drm/i915/glk: Add power wells for GeminilakeAnder Conselvan de Oliveira1-3/+111
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira1-3/+3
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