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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)AuthorFilesLines
2020-10-09drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetchJosé Roberto de Souza1-1/+1
2020-10-09drm/i915/vbt: Add VRR VBT toggleJosé Roberto de Souza1-0/+1
2020-10-09drm/i915/vbt: Update the version and expected size of BDB_GENERAL_DEFINITIONS mapJosé Roberto de Souza1-1/+1
2020-10-09drm/i915/vbt: Fix backlight parsing for VBT 234+José Roberto de Souza2-4/+38
2020-10-09drm/i915: s/int/u32/ for aux_offset/alignmentVille Syrjälä1-2/+2
2020-10-09drm/i915: Skip aux plane stuff when there is no aux planeVille Syrjälä2-10/+17
2020-10-09drm/i915: Set all unused color plane offsets to ~0xfff againVille Syrjälä1-12/+5
2020-10-09drm/i915: Rename i915_{save,restore}_state()Ville Syrjälä3-46/+42
2020-10-09drm/i915: Wait for VLV/CHV/BXT/GLK DSI panel power cycle delay on rebootVille Syrjälä1-0/+8
2020-10-09drm/i915: Wait for LVDS panel power cycle delay on rebootVille Syrjälä1-0/+10
2020-10-09drm/i915: Wait for eDP panel power cycle delay on reboot on all platformsVille Syrjälä3-3/+4
2020-10-09drm/i915: Replace the VLV/CHV eDP reboot notifier with the .shutdown() hookVille Syrjälä2-46/+14
2020-10-09drm/i915: Add an encoder .shutdown() hookVille Syrjälä2-0/+18
2020-10-09drm/i915: Shut down displays gracefully on rebootVille Syrjälä3-0/+25
2020-10-07drm/i915/dg1: provide port/phy mapping for vbtMatt Roper1-3/+5
2020-10-07drm/i915/dg1: Update comp master/slave relationships for PHYsMatt Roper1-2/+2
2020-10-07drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-DMatt Roper1-1/+2
2020-10-07drm/i915/dg1: gmbus pin mappingLucas De Marchi3-4/+24
2020-10-07drm/i915/dg1: Increase mmio size to 4MBVenkata Sandeep Dhanalakota1-0/+4
2020-10-07drm/i915/dg1: Define MOCS table for DG1Lucas De Marchi1-2/+39
2020-10-07drm/i915/dg1: Initialize RAWCLK properlyMatt Roper1-1/+15
2020-10-07drm/i915/display/ehl: Limit eDP to HBR2José Roberto de Souza2-8/+12
2020-10-07drm/i915/gt: Track the most recent pulse for the heartbeatChris Wilson1-3/+3
2020-10-06drm/i915: Fix DMA mapped scatterlist lookupTvrtko Ursulin6-18/+51
2020-10-06drm/i915: Fix DMA mapped scatterlist walksTvrtko Ursulin4-15/+22
2020-10-06drm/i915/gt: Scrub HW state on removeChris Wilson1-5/+6
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak1-16/+25
2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak5-0/+47
2020-10-06drm/i915: Check for unsupported DP link rates during initial commitImre Deak1-0/+12
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak7-16/+78
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak2-0/+14
2020-10-06drm/i915: Skip over MI_NOOP when parsingChris Wilson1-33/+32
2020-10-05lib/scatterlist: Add support in dynamic allocation of SG table from pagesMaor Gottlieb1-6/+6
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper4-0/+23
2020-10-05drm/i915: don't conflate is_dgfx with fake lmemLucas De Marchi2-3/+1
2020-10-02drm/i915: Make lspcon_init() staticVille Syrjälä1-1/+1
2020-10-01drm/i915: Init lspcon after HPD in intel_dp_detect()Kai-Heng Feng5-54/+41
2020-10-01drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä5-70/+76
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä10-325/+386
2020-10-01drm/i915: Split TGL DKL PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split TGL combo PHY buf trans per output typeVille Syrjälä1-34/+49
2020-10-01drm/i915: Split EHL combo PHY buf trans per output typeVille Syrjälä1-20/+39
2020-10-01drm/i915: Split ICL MG PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split ICL combo PHY buf trans per output typeVille Syrjälä1-9/+33
2020-10-01drm/i915: Shove the PHY test into the hotplug workVille Syrjälä1-26/+128
2020-10-01drm/i915: Make intel_dp_process_phy_request() staticVille Syrjälä2-2/+1
2020-10-01drm/i915: s/old_crtc_state/crtc_state/Ville Syrjälä1-2/+2
2020-10-01drm/i915: s/pre_empemph/preemph/Ville Syrjälä1-4/+4
2020-10-01drm/i915: Fix TGL DKL PHY DP vswing handlingVille Syrjälä1-1/+1
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä2-0/+12
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