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path: root/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-09-18drm/msm/dsi: Take advantage of devm_regulator_bulk_get_const()Douglas Anderson1-18/+14
2022-09-18drm/msm/dsi: Don't set a load before disabling a regulatorDouglas Anderson1-3/+3
2022-09-18drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointersMarijn Suijten1-21/+19
2022-09-18drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()Marijn Suijten1-9/+9
2022-09-18drm/msm/dsi/phy: Reindent and reflow multiline function callsMarijn Suijten1-4/+5
2022-05-07drm/msm/dsi: fix address for second DSI PHY on SDM660Dmitry Baryshkov1-1/+1
2022-02-18drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parentMarijn Suijten1-1/+3
2021-10-15drm/msm/dsi: Add phy configuration for MSM8953Vladimir Lypak1-0/+21
2021-10-15drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLLMarijn Suijten1-3/+1
2021-10-11drm/msm/dsi: dsi_phy_14nm: Take ready-bit into account in poll_for_readyMarijn Suijten1-15/+15
2021-08-07drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660Konrad Dybcio1-1/+1
2021-08-07drm/msm/dsi: rename dual DSI to bonded DSIDmitry Baryshkov1-3/+3
2021-06-23drm/msm: Generated register updateRob Clark1-0/+1
2021-04-07drm/msm/dsi: stop passing src_pll_id to the phy_enable callDmitry Baryshkov1-2/+2
2021-04-07drm/msm/dsi: inline msm_dsi_phy_set_src_pllDmitry Baryshkov1-6/+7
2021-04-07drm/msm/dsi: remove temp data from global pll structureDmitry Baryshkov1-225/+109
2021-04-07drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instancesDmitry Baryshkov1-30/+24
2021-04-07drm/msm/dsi: move ioremaps to dsi_phy_driver_probeDmitry Baryshkov1-32/+17
2021-04-07drm/msm/dsi: drop PLL accessor functionsDmitry Baryshkov1-63/+63
2021-04-07drm/msm/dsi: drop msm_dsi_pll abstractionDmitry Baryshkov1-37/+41
2021-04-07drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phyDmitry Baryshkov1-14/+10
2021-04-07drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepareDmitry Baryshkov1-39/+48
2021-04-07drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm driversDmitry Baryshkov1-4/+0
2021-04-07drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocksDmitry Baryshkov1-31/+4
2021-04-07drm/msm/dsi: push provided clocks handling into a generic codeDmitry Baryshkov1-49/+4
2021-04-07drm/msm/dsi: remove msm_dsi_pll_set_usecaseDmitry Baryshkov1-3/+1
2021-04-07drm/msm/dsi: move min/max PLL rate to phy configDmitry Baryshkov1-2/+4
2021-04-07drm/msm/dsi: drop global msm_dsi_phy_type enumarationDmitry Baryshkov1-2/+0
2021-04-07drm/msm/dsi: move all PLL callbacks into PHY config structDmitry Baryshkov1-15/+32
2021-04-07drm/msm/dsi: drop multiple pll enable_seq supportDmitry Baryshkov1-2/+1
2021-04-07drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* codeDmitry Baryshkov1-0/+1089
2021-04-07drm/msm/dsi: replace PHY's init callback with configurable dataDmitry Baryshkov1-17/+2
2020-07-31drm/msm/dsi: Add phy configuration for SDM630/636/660Konrad Dybcio1-0/+18
2019-09-03drm/msm: drop use of drmP.hSam Ravnborg1-0/+2
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner1-9/+1
2018-12-11drm: msm: Use DRM_DEV_* instead of dev_*Mamta Shukla1-3/+3
2017-02-06drm/msm/dsi: Add PHY/PLL for 8x96Archit Taneja1-0/+169
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