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path: root/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2018-03-19drm/msm: rename mdp->dispRob Clark1-779/+0
2017-04-08drm/msm/mdp5: Enable 3D mux in mdp5_ctlArchit Taneja1-2/+7
2017-04-08drm/msm/mdp5: Reset CTL blend registers before configuring themArchit Taneja1-0/+18
2017-04-08drm/msm/mdp5: Stage right side hwpipes on Right-side Layer MixerArchit Taneja1-4/+8
2017-04-08drm/msm/mdp5: Add optional 'right' Layer Mixer in CRTC stateArchit Taneja1-3/+41
2017-04-08drm/msm/mdp5: Remove mixer/intf pointers from mdp5_ctlArchit Taneja1-31/+37
2017-04-08drm/msm/mdp5: Remove the pipeline stuff in mdp5_ctlArchit Taneja1-25/+17
2017-04-08drm/msm/mdp5: Clean up interface assignmentArchit Taneja1-15/+6
2017-04-08drm/msm/mdp5: Start using mdp5_hw_mixerArchit Taneja1-18/+20
2017-02-06drm/msm/mdp5: Misc cursor plane bitsArchit Taneja1-2/+8
2017-02-06drm/msm/mdp5: Prepare CRTC/LM for empty stagesArchit Taneja1-2/+2
2016-07-16drm/msm/mdp5: Use updated MDP5 register namesArchit Taneja1-13/+13
2015-08-15drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSHHai Li1-19/+121
2015-08-15drm/msm/mdp5: Allocate CTL for each display interfaceHai Li1-33/+20
2015-08-15drm/msm/mdp5: Add plane blending operation support for MDP5 (v2)jilai wang1-5/+61
2015-06-11drm/msm: Use customized function to wait for atomic commit doneHai Li1-2/+9
2015-04-01drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau1-11/+0
2015-04-01drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau1-10/+10
2015-04-01drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau1-32/+215
2015-04-01drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau1-10/+81
2015-02-01drm/msm/mdp5: fix parameter type for mdp5_ctl_set_intf()Stephane Viau1-1/+1
2014-11-21drm/msm/mdp5: remove global mdp5_ctl_mgrRob Clark1-10/+16
2014-11-21drm/msm/mdp5: don't use void * for opaque typesRob Clark1-23/+14
2014-11-21drm/msm: add multiple CRTC and overlay supportStephane Viau1-0/+325
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