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path: root/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-02-11drm/nouveau/sec2: switch to instanced constructorBen Skeggs1-2/+3
2020-07-24drm/nouveau/sec2/gp102: allow module to load when LSFW is missingBen Skeggs1-2/+11
2020-07-24drm/nouveau/acr: store a mask of LS falcons the controlling LSFW can bootstrapBen Skeggs1-0/+6
2020-07-24drm/nouveau/nvfw: firmware structures should begin with nvfw_Timur Tabi1-1/+1
2020-01-15drm/nouveau/acr: implement new subdev to replace "secure boot"Ben Skeggs1-0/+72
2020-01-15drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs1-0/+12
2020-01-15drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs1-0/+32
2020-01-15drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs1-0/+44
2020-01-15drm/nouveau/flcn: reset sec2/gsp falcons harderBen Skeggs1-1/+10
2020-01-15drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs1-0/+2
2020-01-15drm/nouveau/flcn: specify debug/production register offset from subdevBen Skeggs1-0/+1
2020-01-15drm/nouveau/flcn: specify EMEM address from subdevBen Skeggs1-0/+1
2020-01-15drm/nouveau/flcn: move bind_context WAR out of common codeBen Skeggs1-1/+41
2020-01-15drm/nouveau/flcn: specify FBIF offset from subdevBen Skeggs1-0/+1
2020-01-15drm/nouveau/sec2: move interrupt handler to hw-specific moduleBen Skeggs1-0/+20
2020-01-15drm/nouveau/sec2: initialise SW state for falcon from constructorBen Skeggs1-1/+17
2020-01-15drm/nouveau/sec2: select implementation based on available firmwareBen Skeggs1-4/+58
2019-02-20drm/nouveau/sec2: utilise engine PRI address from TOPBen Skeggs1-1/+1
2017-03-07drm/nouveau/core: add SEC2 engineAlexandre Courbot1-0/+30
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