aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/rockchip/rockchip_drm_vop.h (follow)
AgeCommit message (Collapse)AuthorFilesLines
2022-09-15drm/rockchip: define gamma registers for RK3399Hugh Cole-Baker1-0/+2
The VOP on RK3399 has a different approach from previous versions for setting a gamma lookup table, using an update_gamma_lut register. As this differs from RK3288, give RK3399 its own set of "common" register definitions. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Tested-by: "Milan P. Stanić" <mps@arvanta.net> Tested-by: Linus Heckemann <git@sphalerite.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-2-sigmaris@gmail.com
2022-05-04drm/rockchip: Add VOP2 driverAndy Yan1-0/+14
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568. It replaces the VOP unit found in the older Rockchip SoCs. This driver has been derived from the downstream Rockchip Kernel and heavily modified: - All nonstandard DRM properties have been removed - dropped struct vop2_plane_state and pass around less data between functions - Dropped all DRM_FORMAT_* not known on upstream - rework register access to get rid of excessively used macros - Drop all waiting for framesyncs The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB board. Overlay support is tested with the modetest utility. AFBC support on the cluster windows is tested with weston-simple-dmabuf-egl on weston using the (yet to be upstreamed) panfrost driver support. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Co-Developed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> [dt-binding-header:] Acked-by: Rob Herring <robh@kernel.org> [moved dt-binding header from dt-nodes patch to here and made checkpatch --strict happier] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de
2022-05-03drm/rockchip: Support YUV formats with U/V swappedChen-Yu Tsai1-0/+1
The VOP in Rockchip SoCs that support YUV planes also support swapping of the U and V elements. Supporting the swapped variants, especially NV21, would be beneficial for multimedia applications, as the hardware video decoders only output NV21, and supporting this pixel format in the display pipeline would allow the decoded video frames to be output directly. Add support for this to support the various formats that have U/V swapped. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220114074038.2633848-1-wenst@chromium.org
2021-02-25drm/rockchip: Require the YTR modifier for AFBCAlyssa Rosenzweig1-0/+11
The AFBC decoder used in the Rockchip VOP assumes the use of the YUV-like colourspace transform (YTR). YTR is lossless for RGB(A) buffers, which covers the RGBA8 and RGB565 formats supported in vop_convert_afbc_format. Use of YTR is signaled with the AFBC_FORMAT_MOD_YTR modifier, which prior to this commit was missing. As such, a producer would have to generate buffers that do not use YTR, which the VOP would erroneously decode as YTR, leading to severe visual corruption. The upstream AFBC support was developed against a captured frame, which failed to exercise modifier support. Prior to bring-up of AFBC in Mesa (in the Panfrost driver), no open userspace respected modifier reporting. As such, this change is not expected to affect broken userspaces. Tested on RK3399 with Panfrost and Weston. Fixes: 7707f7227f09 ("drm/rockchip: Add support for afbc") Cc: stable@vger.kernel.org Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Acked-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200811202631.3603-1-alyssa.rosenzweig@collabora.com Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2020-06-17drm/rockchip: Add per-pixel alpha support for the PX30 VOPPaul Kocialkowski1-0/+3
Compared to its predecessors, the PX30 VOP has a different register layout for enabling per-pixel alpha. Instead of src_alpha_ctl and dst_alpha_ctl, there is a single alpha control register. This register takes some fields from src_alpha_ctl, but with a different layout. Add support for the required fields to the PX30 VOP window descriptions, which makes per-pixel-alpha formats behave correctly. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200416140526.262533-1-paul.kocialkowski@bootlin.com
2020-03-23drm/rockchip: Add support for afbcAndrzej Pietrasiewicz1-0/+17
This patch adds support for afbc handling. afbc is a compressed format which reduces the necessary memory bandwidth. Co-developed-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com> Reviewed-by: Sandy Huang <hjc@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200311145541.29186-7-andrzej.p@collabora.com
2020-01-13drm/rockchip: use DIV_ROUND_UP macro for calculations.Wambui Karuga1-1/+1
Replace the open coded calculation with the more concise and readable DIV_ROUND_UP macro. Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200109142057.10744-1-wambui.karugax@gmail.com
2019-10-13drm/rockchip: vop: add the definition of dclk_polNickey Yang1-2/+6
Some VOP's (such as px30) dclk_pol bit is at the last. So it is necessary to distinguish dclk_pol and pin_pol. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-by: Sandy Huang <hjc@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20191010034452.20260-2-nickey.yang@rock-chips.com
2019-10-11drm/rockchip: Add optional support for CRTC gamma LUTEzequiel Garcia1-0/+2
Add an optional CRTC gamma LUT support, and enable it on RK3288. This is currently enabled via a separate address resource, which needs to be specified in the devicetree. The address resource is required because on some SoCs, such as RK3288, the LUT address is after the MMU address, and the latter is supported by a different driver. This prevents the DRM driver from requesting an entire register space. The current implementation works for RGB 10-bit tables, as that is what seems to work on RK3288. Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191010194351.17940-3-ezequiel@collabora.com
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-03-30drm/rockchip: vop: Support dithering to RGB666Urja Rannikko1-1/+13
Splits out the dither register bits and introduces the same config enumerations as in the rockchip kernel tree. Tested to fix the banding on my ASUS C201. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20190318154412.26994-1-urjaman@gmail.com
2019-01-11drm/rockchip: Add reflection propertiesDaniele Castagna1-0/+2
Add the KMS plane rotation property to the DRM rockchip driver, for SoCs RK3328, RK3368 and RK3399. RK3288 only supports rotation at the display level (i.e. CRTC), but for now we are only interested in plane rotation. This commit only adds support for the value of reflect-y and reflect-x (i.e. mirroring). Note that y-mirroring is not compatible with YUV. The following modetest commands would test this feature, where 30 is the plane ID, and 49 = rotate_0 + relect_y + reflect_x. X mirror: modetest -s 43@33:1920x1080@XR24 -w 30:rotation:17 Y mirror: modetest -s 43@33:1920x1080@XR24 -w 30:rotation:33 XY mirror: modetest -s 43@33:1920x1080@XR24 -w 30:rotation:49 Signed-off-by: Daniele Castagna <dcastagna@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20190109185639.5093-4-ezequiel@collabora.com
2019-01-10drm/rockchip: Fix YUV buffers color renderingDaniele Castagna1-0/+13
Currently, YUV hardware overlays are converted to RGB using a color space conversion different than BT.601. The result is that colors of e.g. NV12 buffers don't match colors of YUV hardware overlays. In order to fix this, enable YUV2YUV and set appropriate coefficients for formats such as NV12 to be displayed correctly. This commit was tested using modetest, gstreamer and chromeos (hardware accelerated video playback). Before the commit, tests rendering with NV12 format resulted in colors not displayed correctly. Test examples (Tested on RK3399 and RK3288 boards connected to HDMI monitor): $ modetest 39@32:1920x1080@NV12 $ gst-launch-1.0 videotestrc ! video/x-raw,format=NV12 ! kmssink Signed-off-by: Daniele Castagna <dcastagna@chromium.org> [ezequiel: rebase on linux-next and massage commit log] Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20190108214659.28794-1-ezequiel@collabora.com
2018-10-30drm/rockchip: dsi: add dual mipi supportHeiko Stuebner1-0/+4
Add the Rockchip-sepcific dual-dsi setup and hook it into the VOP as well. As described in the general dual-dsi devicetree binding, the panel should define two input ports and point each of them to one of the used dsi- controllers, as well as declare one of them as clock-master. This is used to determine the dual-dsi state and get access to both controller instances. v6: handle master+slave component in dsi-attach v5: use driver-internal mechanism to find dual dsi slave v4: add component directly in probe when adding empty dsi slave controller Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181001123845.11818-8-heiko@sntech.de
2018-09-05drm/rockchip: Add support for Rockchip Soc RGB output interfaceSandy Huang1-0/+1
Some Rockchip CRTCs, like rv1108 and px30, can directly output parallel and serial RGB data to panel or conversion chip. So add a feature-bit for vops to mark the ability for these direct outputs and add an internal encoder in that case, that can attach to bridge chipsor panels. Changes in v7: 1. forget to delete rockchip_rgb_driver and delete it. Changes in v6: 1. Update according to Heiko Stuebner' implemention, rgb output is part of vop's feature, should not register as a independent driver. Changes in v5: 1. add SPDX-License-Identifier tag Changes in v4: 1. add support px30; Changes in v3: 1. update for rgb-mode move to panel node. Changes in v2: 1. add error log when probe failed; 2. update name_to_output_mode() according to sean's suggest; 3. Fix uninitialized use of ret. Signed-off-by: Sandy Huang <hjc@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180830211207.10480-3-heiko@sntech.de
2018-06-27drm/rockchip: vop: fixup linebuffer mode calc errorSandy Huang1-10/+13
linebuffer mode should be LB_YUV_3840X5 when width is bigger than 1280 in yuv mode. Separate yuv and rgb case makes the scl_vop_cal_lb_mode() logic clearer. Signed-off-by: Sandy Huang <hjc@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1530001004-25036-1-git-send-email-hjc@rock-chips.com
2018-04-24drm/rockchip: pre dither down when output bpc is 8bitMark Yao1-0/+1
Some encoder have a crc verification check, crc check fail if input and output data is not equal. That means encoder input and output need use same color depth, vop can output 10bit data to encoder, but some panel only support 8bit depth, that would make crc check die. So pre dither down vop data to 8bit if panel's bpc is 8. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict in rockchip_drm_vop.c] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-22-enric.balletbo@collabora.com
2017-08-04drm/rockchip: vop: fix NV12 video display errorMark yao1-0/+3
fixup the scale calculation formula on the case src_height == (dst_height/2). Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Sandy huang <sandy.huang@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/1501494586-6984-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: rk3328: fix overlay abnormalMark yao1-0/+1
It's a hardware bug, all window's overlay channel reset value is same, hardware overlay would be die. so we must initial difference id for each overlay channel. The Channel register is supported on all vop will full design. Following is the details for this register VOP_WIN0_CTRL2 bit[7:4] win_rid_win0_cbr axi read id of win0 cbr channel bit[3:0] win_rid_win0_yrgb axi read id of win0 yrgb channel Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1501049980-6239-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: add a series of vop supportMark yao1-0/+9
Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328 The above IP version is from H/W define, some of vop support get the IP version from VERSION_INFO register, some are not. hardcode the IP version for each vop to identify them. major version: used for IP structure, Vop full framework is 3, vop little framework is 2. minor version: on same structure, newer design vop will bigger then old one. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1501049971-6131-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: group vop registersMark yao1-25/+35
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1501221986-29722-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: move line_flag_num to interrupt registersMark yao1-2/+2
In the hardware design process, the design of line flags register is associated with the interrupt register, placing the line flags in the interrupt definition is more reasonable, and it would make multi-vop define easilier. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1501049960-6006-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: move write_relaxed flags to vop registerMark yao1-0/+1
Since the drm atomic framework, only a small part of the vop register needs sync write, Currently seems only following registers need sync write: cfg_done, standby and interrupt related register. All ctrl registers are using the sync write method that is inefficient, hardcode the write_relaxed flags to vop registers, then can only do synchronize write for those actual needed register. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/1501049953-5946-1-git-send-email-mark.yao@rock-chips.com
2017-07-31drm/rockchip: vop: initialize registers directlyMark yao1-7/+3
At present we are using init_table to initialize some registers, but the Register init table use un-document define, it is unreadable, and sometimes we only want to update tiny bits, init table method is not friendly, it's diffcult to reuse for difference chips. To make it clean, initialize registers directly, and drops init_table mechanism out. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Link: https://patchwork.freedesktop.org/patch/msgid/1501049946-5877-1-git-send-email-mark.yao@rock-chips.com
2017-05-31drm/rockchip: Correct vop out_mode configureMark yao1-0/+3
Force vop output mode on encoder driver seem not a good idea, EDP, HDMI, DisplayPort all have 10bit input on rk3399, On non-10bit vop, vop 8bit output bit[0-7] connect to the encoder high 8bit [2-9]. So force RGB10 to RGB888 on vop driver would be better. And another problem, EDP check crtc id on atomic_check, but encoder maybe NULL, so out_mode configure would fail, it cause edp no display. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com> Link: http://patchwork.freedesktop.org/patch/msgid/1495885416-22216-1-git-send-email-mark.yao@rock-chips.com
2017-02-05drm/rockchip: cdn-dp: add cdn DP support for rk3399Chris Zhong1-0/+9
Add support for cdn DP controller which is embedded in the rk3399 SoCs. The DP is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/rockchip/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The dclk pin_pol of vop must not be invert for DP. Signed-off-by: Chris Zhong <zyw@rock-chips.com> [seanpaul fixed up some races between the worker and modeset] [seanpaul squashed ~15 commits from chromium.org gerrit] Signed-off-by: Sean Paul <seanpaul@chromium.org> [groeck fixed compilation errors when building as module] Signed-off-by: Guenter Roeck <groeck@chromium.org>
2016-08-23drm/rockchip: vop: export line flag functionYakir Yang1-0/+2
VOP have integrated a hardware counter which indicate the exact display line that vop is scanning. And if we're interested in a specific line, we can set the line number to vop line_flag register, and then vop would generate a line_flag interrupt for it. For example eDP PSR function is interested in the vertical blanking period, then driver could set the line number to zero. This patch have exported a symbol that allow other driver to listen the line flag event with given timeout limit: - rockchip_drm_wait_line_flag() Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2016-08-23drm/rockchip: vop: add rk3399 vop supportMark Yao1-0/+4
There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the Major differences of this two is that: VOP_BIG max output resolution is 4096x2160. VOP_LIT max output resolution is 2560x1600 VOP_BIG support four windows. VOP_LIT only support two windows. RK3399 vop register layout is similar with rk3288, so some feature can reuse with rk3288. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2016-08-23drm/rockchip: vop: introduce VOP_REG_MASKMark Yao1-0/+1
Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul masked 'v' per tfiga's review comments] Reviewed-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2015-12-28drm/rockchip: vop: spilt scale regstersMark Yao1-2/+12
There are two version scale control register found on vop, scale full version found on rk3288, support extension registers. and scale little version found on rk3036, only support common scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-12-28drm/rockchip: vop: spilt register related into rockchip_reg_vop.cMark Yao1-105/+115
No functional updates. Spilt register related into another file would be nice to multi vop driver, Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: support plane scaleMark Yao1-0/+88
Win_full support 1/8 to 8 scale down/up engine, support all format scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2014-12-02drm: rockchip: Add basic drm driverMark Yao1-0/+201
This patch adds the basic structure of a DRM Driver for Rockchip Socs. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.