aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/tegra/dc.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2015-01-27drm/tegra: dc: Unify enabling the display controllerThierry Reding1-0/+12
2015-01-27drm/tegra: Track tiling and format in plane stateThierry Reding1-28/+99
2015-01-27drm/tegra: Track active planes in CRTC stateThierry Reding1-28/+44
2015-01-27drm/tegra: Atomic conversion, phase 3, step 3Thierry Reding1-118/+11
2015-01-27drm/tegra: Atomic conversion, phase 3, step 2Thierry Reding1-1/+1
2015-01-27drm/tegra: dc: Use atomic clock state in modesetThierry Reding1-0/+37
2015-01-27drm/tegra: dc: Store clock setup in atomic stateThierry Reding1-3/+68
2015-01-27drm/tegra: Atomic conversion, phase 3, step 1Thierry Reding1-6/+6
2015-01-27drm/tegra: Atomic conversion, phase 2Thierry Reding1-0/+12
2015-01-27drm/tegra: Atomic conversion, phase 1Thierry Reding1-184/+213
2015-01-27drm/tegra: dc: Do not needlessly deassert resetThierry Reding1-4/+0
2015-01-27drm/tegra: Remove remnants of the output midlayerThierry Reding1-52/+0
2015-01-27drm/tegra: rgb: DemidlayerThierry Reding1-0/+24
2015-01-27drm/tegra: Add tegra_dc_setup_clock() helperThierry Reding1-0/+20
2015-01-27drm/tegra: output: Make ->setup_clock() optionalThierry Reding1-1/+9
2015-01-27drm/tegra: dc: No longer disable planes at CRTC disableThierry Reding1-14/+0
2015-01-27drm/tegra: dc: Wait for idle when disabledThierry Reding1-5/+65
2015-01-27drm/tegra: Stop CRTC at CRTC disable timeThierry Reding1-0/+6
2015-01-27drm/tegra: Use tegra_commit_dc() in output driversThierry Reding1-1/+1
2015-01-27drm/tegra: dc: Fix bad irqsave/restore in tegra_dc_finish_page_flip()Dan Carpenter1-2/+2
2015-01-27drm/tegra: dc: Return planar flag for non-YUV modesThierry Reding1-0/+3
2015-01-27drm/tegra: dc: Describe register copiesThierry Reding1-0/+12
2015-01-27drm/tegra: dc: Initialize border colorThierry Reding1-0/+8
2015-01-27drm/tegra: plane: Use proper possible_crtcs maskThierry Reding1-1/+14
2015-01-27drm/tegra: Remove redundant zeroing out of memoryThierry Reding1-6/+0
2015-01-09Merge tag 'topic/core-stuff-2014-12-19' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie1-5/+0
2014-12-17drm/tegra: dc: Select root window for event dispatchSean Paul1-2/+22
2014-12-17drm/tegra: dc: Fix a potential race on page-flip completionThierry Reding1-3/+7
2014-12-17drm/tegra: dc: Consistently use the same pipeThierry Reding1-7/+7
2014-12-10drm/tegra: Remove dummy ->load_lut() implementationThierry Reding1-5/+0
2014-12-02Merge tag 'v3.18-rc7' into drm-nextDave Airlie1-4/+4
2014-11-15Merge tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux into drm-nextDave Airlie1-180/+413
2014-11-13drm/tegra: dc: Universal plane supportThierry Reding1-157/+330
2014-11-13drm/tegra: dc: Registers are 32 bits wideThierry Reding1-1/+1
2014-11-13drm/tegra: dc: Factor out DC, window and cursor commitThierry Reding1-24/+28
2014-11-13drm/tegra: Add IOMMU supportThierry Reding1-0/+17
2014-11-13drm/tegra: dc: Add powergate supportThierry Reding1-3/+42
2014-11-13drm/tegra: dc: Add missing call to drm_vblank_on()Thierry Reding1-5/+4
2014-11-05drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.hDaniel Vetter1-0/+2
2014-08-04drm/tegra: add MODULE_DEVICE_TABLEsStephen Warren1-0/+1
2014-08-04drm/tegra: dc - Reset controller on driver removeThierry Reding1-0/+1
2014-08-04drm/tegra: Properly align stride for framebuffersThierry Reding1-0/+19
2014-08-04drm/tegra: Implement more tiling modesThierry Reding1-15/+87
2014-06-05drm/tegra: Add hardware cursor supportThierry Reding1-0/+111
2014-06-05drm/tegra: Remove host1x drm_bus implementationThierry Reding1-5/+5
2014-06-05drm/tegra: dc - Compute shift clock divider in output driversThierry Reding1-8/+5
2014-06-05drm/tegra: dc - Move around shift clock programmingThierry Reding1-9/+10
2014-06-05drm/tegra: dc - Use proper H/V ref-to-sync valuesThierry Reding1-3/+2
2014-06-05drm/tegra: dc - Do not touch power control registerThierry Reding1-4/+0
2014-06-05drm/tegra: dc - Reshuffle code to get rid of prototypesThierry Reding1-248/+248
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.