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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2020-09-03drm/amdgpu: disable gpu-sched load balance for uvdNirmoy Das1-1/+5
2020-09-03drm/managed: Cleanup of unused functions and polishing docsDaniel Vetter2-58/+22
2020-09-03drm/i915: fix regression leading to display audio probe failure on GLKKai Vehmanen1-6/+4
2020-09-03drm/ttm: remove io_reserve_lru handling v3Christian König4-169/+24
2020-09-03drm/nouveau: move io_reserve_lru handling into the driver v5Christian König4-23/+127
2020-09-03drm/ttm: make sure that we always zero init mem.bus v2Christian König1-0/+9
2020-09-03drm/nouveau/kms/nv50-gp1xx: add WAR for EVO push buffer HW bugBen Skeggs1-0/+6
2020-09-03drm/nouveau/kms/nv50-gp1xx: disable notifies again after core updateBen Skeggs1-1/+4
2020-09-03drm/nouveau/kms/nv50-: add some whitespace before debug messageBen Skeggs1-1/+1
2020-09-03drm/nouveau/kms/gv100-: Include correct push header in crcc37d.cLyude Paul1-1/+1
2020-09-03drm/radeon: Prefer lower feedback dividersKai-Heng Feng1-1/+1
2020-09-03drm/amdgpu: Fix bug in reporting voltage for CIKSandeep Raghuraman1-1/+2
2020-09-03drm/amdgpu: Specify get_argument function for ci_smu_funcsSandeep Raghuraman1-0/+2
2020-09-03drm/amd/pm: enable MP0 DPM for sienna_cichlidJiansong Chen1-1/+3
2020-09-03drm/amd/pm: avoid false alarm due to confusing softwareshutdowntemp settingEvan Quan1-2/+12
2020-09-03drm/amd/pm: fix is_dpm_running() run error on 32bit systemKevin Wang3-9/+21
2020-09-02drm/i915: Clear the repeater bit on HDCP disableSean Paul1-0/+6
2020-09-02drm/i915: Fix sha_text population codeSean Paul1-6/+20
2020-09-02drm/i915/display: Ensure that ret is always initialized in icl_combo_phy_verify_stateNathan Chancellor1-2/+2
2020-09-02drm/virtio: fix unblankGerd Hoffmann3-1/+15
2020-09-02drm/virtio: drop virtio_gpu_output->enabledGerd Hoffmann3-6/+1
2020-09-02drm/virtio: fix unblankGerd Hoffmann3-1/+15
2020-09-01drm/gma500: Constify static structsRikard Falkeborn1-3/+3
2020-09-01drm: Replace mode->export_head with a booleanVille Syrjälä1-13/+32
2020-09-01drm/dp_mst: Support remote i2c writesSam McNally1-16/+90
2020-09-01drm/crc-debugfs: Fix memleak in crc_control_writeDinghao Liu1-1/+3
2020-09-01drm/i915: Add HDCP 1.4 support for MST connectorsSean Paul3-2/+84
2020-09-01drm/i915: Print HDCP version info for all connectorsSean Paul1-12/+9
2020-09-01drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband messageSean Paul2-0/+167
2020-09-01drm/i915: Add connector to hdcp_shim->check_link()Sean Paul4-8/+10
2020-09-01drm/i915: Plumb port through hdcp initSean Paul4-8/+10
2020-09-01drm/i915: Factor out HDCP shim functions from dp for use by dp_mstSean Paul4-606/+642
2020-09-01drm/i915: Use ddi_update_pipe in intel_dp_mstSean Paul3-5/+13
2020-09-01drm/i915: Support DP MST in enc_to_dig_port() functionSean Paul1-7/+14
2020-09-01drm/i915: Don't fully disable HDCP on a port if multiple pipes are using itSean Paul5-0/+45
2020-09-01drm/i915: Clean up intel_hdcp_disableSean Paul1-9/+10
2020-09-01drm/i915: Protect workers against disappearing connectorsSean Paul1-5/+39
2020-09-01drm/i915: Factor out hdcp->value assignmentsSean Paul1-21/+46
2020-09-01drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signallingSean Paul6-22/+26
2020-09-01drm/i915: Intercept Aksv writes in the aux hooksSean Paul1-33/+29
2020-09-01drm/i915: WARN if HDCP signalling is enabled upon disableSean Paul1-0/+2
2020-09-01drm/i915: Clear the repeater bit on HDCP disableSean Paul1-0/+6
2020-09-01drm/i915: Fix sha_text population codeSean Paul1-6/+20
2020-08-31drm/nouveau/kms: Start using drm_dp_read_dpcd_caps()Lyude Paul1-8/+6
2020-08-31drm/i915/dp: Extract drm_dp_read_dpcd_caps()Lyude Paul4-60/+80
2020-08-31drm/nouveau/kms: Don't change EDID when it hasn't actually changedLyude Paul1-27/+27
2020-08-31drm/nouveau/kms/nv50-: Add support for DP_SINK_COUNTLyude Paul2-5/+50
2020-08-31drm/i915/dp: Extract drm_dp_read_sink_count()Lyude Paul2-6/+31
2020-08-31drm/i915/dp: Extract drm_dp_read_sink_count_cap()Lyude Paul2-9/+34
2020-08-31drm/nouveau/kms/nv50-: Use downstream DP clock limits for mode validationLyude Paul3-4/+15