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2017-04-12drm/i915: Convert intel_dp_mst connector properties to atomic.Maarten Lankhorst1-10/+1
2017-04-12drm/i915: Remove unused dp properties for dp-mst.Maarten Lankhorst3-3/+1
2017-04-12drm/i915: Convert intel_tv connector properties to atomic, v5.Maarten Lankhorst1-112/+63
2017-04-12drm/i915: Remove unused members from intel_tv.cMaarten Lankhorst1-33/+0
2017-04-12drm/i915/execlists: Document runtime pm for intel_lrc_irq_handler()Chris Wilson1-0/+9
2017-04-12Merge airlied/drm-next into drm-intel-next-queuedDaniel Vetter581-7938/+412387
2017-04-11drm/i915: Lie and treat all engines as idle if wedgedChris Wilson1-0/+4
2017-04-11drm/i915: Use the engine class to get the context sizeDaniele Ceraolo Spurio1-10/+19
2017-04-11drm/i915: Bail if we do not setup the RCS engineChris Wilson1-2/+8
2017-04-11drm/i915/dp: read sink count to a temporary variable firstJani Nikula1-3/+4
2017-04-11drm/i915/dp: use readb and writeb calls for single byte DPCD accessJani Nikula1-20/+17
2017-04-11drm/i915/dp: localize link rate index variable moreJani Nikula1-6/+7
2017-04-11drm/i915/mst: use max link not sink lane countJani Nikula3-3/+4
2017-04-11drm/i915/dp: add functions for max common link rate and lane countJani Nikula1-12/+17
2017-04-11drm/i915/dp: don't call the link parameters sink parametersJani Nikula2-17/+16
2017-04-11drm/i915/dp: do not limit rate seek when not neededJani Nikula1-19/+12
2017-04-11drm/i915/dp: cache common rates with sink ratesJani Nikula2-33/+45
2017-04-11drm/i915/dp: use the sink rates array for max sink ratesJani Nikula2-22/+8
2017-04-11drm/i915: Rename intel_engine_cs.exec_id to uabi_idChris Wilson4-13/+13
2017-04-11drm/i915: Split the engine info table in two levels, using class + instanceOscar Mateo1-23/+43
2017-04-11drm/i915: Generate the engine name based on the instance numberOscar Mateo3-4/+7
2017-04-11drm/i915: Use the same vfunc for BSD2 ring initOscar Mateo3-16/+1
2017-04-11drm/i915: Classify the engines in class + instanceDaniele Ceraolo Spurio3-0/+26
2017-04-11drm/i915: Use safer intel_uncore_wait_for_register in ring-initChris Wilson1-3/+3
2017-04-11drm/i915: Use __intel_uncore_wait_for_register_fw for sandybride_pcode_readChris Wilson1-6/+6
2017-04-11drm/i915: Acquire uncore.lock over intel_uncore_wait_for_register()Chris Wilson1-4/+12
2017-04-11drm/i915: Stop sleeping from inside gen6_bsd_submit_request()Chris Wilson1-5/+5
2017-04-11drm/i915: Stop second guessing the caller for intel_uncore_wait_for_register()Chris Wilson1-5/+7
2017-04-11Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-nextDave Airlie34-622/+1568
2017-04-11Merge tag 'drm-misc-next-2017-04-07' of git://anongit.freedesktop.org/git/drm-misc into drm-nextDave Airlie107-1864/+4555
2017-04-11Backmerge tag 'v4.11-rc6' into drm-nextDave Airlie21-89/+150
2017-04-11Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie27-220/+455
2017-04-11Merge tag 'drm-intel-testing-2017-04-03' of git://anongit.freedesktop.org/git/drm-intel into drm-nextDave Airlie60-1997/+2601
2017-04-10drm/i915: Don't allow overuse of __intel_wait_for_register_fw()Michal Wajdeczko1-0/+5
2017-04-10drm/i915: Drop const qualifiers from params in wait_for_register()Michal Wajdeczko2-17/+17
2017-04-10drm/i915: Use drm_i915_private directly from debugfsChris Wilson1-6/+4
2017-04-08msm/drm: gpu: Dynamically locate the clocks from the device treeJordan Crouse2-24/+58
2017-04-08drm/msm: gpu: Use OPP tables if we canJordan Crouse1-19/+66
2017-04-08drm/msm: Hard code the GPU "slow frequency"Jordan Crouse5-11/+11
2017-04-08drm/msm: Add MSM_PARAM_GMEM_BASEJordan Crouse1-0/+3
2017-04-08drm/msm: Reference count address spacesJordan Crouse6-13/+33
2017-04-08drm/msm: Make sure to detach the MMU during GPU cleanupJordan Crouse2-13/+19
2017-04-08drm/msm/mdp5: Enable 3D mux in mdp5_ctlArchit Taneja1-2/+7
2017-04-08drm/msm/mdp5: Reset CTL blend registers before configuring themArchit Taneja1-0/+18
2017-04-08drm/msm/mdp5: Assign 'right' mixer to CRTC stateArchit Taneja3-22/+129
2017-04-08drm/msm/mdp5: Stage border out on base stage if CRTC has 2 LMsArchit Taneja1-10/+35
2017-04-08drm/msm/mdp5: Stage right side hwpipes on Right-side Layer MixerArchit Taneja2-4/+20
2017-04-08drm/msm/mdp5: Prepare Layer Mixers for source splitArchit Taneja1-7/+32
2017-04-08drm/msm/mdp5: Configure 'right' hwpipeArchit Taneja2-1/+46
2017-04-08drm/msm/mdp5: Assign a 'right hwpipe' to plane stateArchit Taneja2-1/+57
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