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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2021-01-26drm/i915/selftest: Fix potential memory leakPan Bian1-1/+1
2021-01-26drm/i915: Check for all subplatform bitsUmesh Nerlige Ramappa1-1/+1
2021-01-26drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-26drm/i915/gt: Clear CACHE_MODE prior to clearing residualsChris Wilson1-0/+12
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä2-6/+48
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä5-270/+139
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä1-55/+88
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä2-11/+12
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä1-37/+18
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2-16/+21
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
2021-01-25drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
2021-01-25drm/i915: Fix vblank timestamps with VRRVille Syrjälä4-6/+34
2021-01-25drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
2021-01-25drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
2021-01-25drm/i915/display: Add HW state readout for VRRManasi Navare3-0/+26
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2-1/+20
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare3-0/+16
2021-01-25drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare3-0/+18
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare3-0/+28
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä1-7/+7
2021-01-25drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä1-0/+3
2021-01-25drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare1-0/+7
2021-01-25drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare5-0/+95
2021-01-25drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä1-14/+24
2021-01-25drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä1-3/+11
2021-01-25drm/i915: Store framestart_delay in dev_privVille Syrjälä2-11/+14
2021-01-25drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup2-2/+10
2021-01-25drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare4-0/+49
2021-01-25drm/amd/display: Fix HDMI deep color output for DCE 6-11.Mario Kleiner3-0/+76
2021-01-25drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction.Mario Kleiner1-4/+4
2021-01-25amdgpu: fix clang build warningArnd Bergmann3-4/+8
2021-01-25drm/amd/display: Fix a potential NULL dereferenceDan Carpenter1-2/+2
2021-01-25drm/amd/display: change license of color_table.cJonathan Gray1-5/+21
2021-01-25drm/amdgpu: Fix masking binary not operator on two mask operationsColin Ian King1-2/+2
2021-01-25drm/amd/pm: store and reinstate swsmu user power configurationsArunpravin2-4/+159
2021-01-25drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_dataJingwen Chen1-1/+5
2021-01-25drm/amd/display: fix 64-bit division issue on 32-bit OSLang Yu1-6/+6
2021-01-25Revert "drm/amd/display: Tune min clk values for MPO for RV"Pratik Vishwakarma1-27/+3
2021-01-25drm/amdgpu: race issue when jobs on 2 ring timeoutHorace Chen1-10/+59
2021-01-25drm/amdgpu: Make contiguous pinning optionalFelix Kuehling1-1/+6
2021-01-25drm/gma500: Get rid of duplicate NULL checksAndy Shevchenko1-12/+6
2021-01-25drm/gma500: Convert to use new SCU IPC APIAndy Shevchenko7-14/+17
2021-01-25drm/etnaviv: fix NULL check before some freeing functions is not neededTian Tao1-2/+1
2021-01-25drm/vc4: Correct POS1_SCL for hvs5Dom Cobley1-2/+2
2021-01-25drm/vc4: Correct lbm size and calculationDom Cobley2-5/+10
2021-01-25Merge tag 'v5.11-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-nextDave Airlie93-170/+1278
2021-01-24drm/doc: document the type plane propertySimon Ser1-4/+54
2021-01-22drm/panfrost: Add governor data with pre-defined thresholdsLukasz Luba2-1/+11
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