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AgeCommit message (Expand)AuthorFilesLines
2021-01-14drm/amd/display/dmub/src/dmub_dcn30: Include our own header containing prototypesLee Jones1-0/+1
2021-01-14drm/amd/include/renoir_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
2021-01-14drm/amd/display/dc/dc_helper: Include our own header, containing prototypesLee Jones1-0/+1
2021-01-14drm/amd/display/dc/calcs/dce_calcs: Demote non-conformant kernel-doc function headersLee Jones1-3/+2
2021-01-14drm/amd/display/dc/calcs/dce_calcs: Remove unused variables 'v_filter_init_mode' and 'sclk_lvl'Lee Jones1-7/+1
2021-01-14drm/amd/display: Fix to be able to stop crc calculationWayne Lin1-1/+1
2021-01-14Revert "drm/amd/display: Expose new CRC window property"Rodrigo Siqueira4-210/+10
2021-01-14Revert "drm/amdgpu/disply: fix documentation warnings in display manager"Rodrigo Siqueira1-20/+1
2021-01-14Revert "drm/amd/display: Fix unused variable warning"Rodrigo Siqueira2-2/+4
2021-01-14drm/amd/pm: modify the fine grain tuning function for vangoghXiaojian Du2-6/+48
2021-01-14drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du4-23/+6
2021-01-14drm/amdgpu: set power brake sequenceLikun Gao1-0/+32
2021-01-14drm/modes: Switch to 64bit maths to avoid integer overflowVille Syrjälä1-2/+2
2021-01-14drm/vmwgfx: Fix display register usage for some older configsZack Rusin2-2/+2
2021-01-14drm/vmwgfx: Cleanup the cmd/fifo splitZack Rusin23-207/+198
2021-01-14drm/vmwgfx: Remove the throttling codeZack Rusin6-188/+3
2021-01-14drm/vmwgfx: Cleanup pci resource allocationZack Rusin2-45/+73
2021-01-14drm/vmwgfx: Cleanup fifo mmio handlingZack Rusin7-111/+96
2021-01-14drm/vmwgfx: Switch to a managed drm deviceZack Rusin10-84/+68
2021-01-14drm/vmwgfx: Remove stealth modeZack Rusin2-26/+10
2021-01-14drm/i915/dg1: Apply WA 1409120013 and 14011059788José Roberto de Souza1-5/+7
2021-01-14drm/i915/gt: Prune inlinesChris Wilson13-29/+28
2021-01-14drm/i915/gt: Prune 'inline' from execlistsChris Wilson1-34/+29
2021-01-14drm/vblank: Fix typo in docsSumera Priyadarsini1-1/+1
2021-01-14drm/i915/gt: Reapply ppgtt enabling after engine resetsChris Wilson2-12/+10
2021-01-14drm/sun4i: tcon: fix inverted DCLK polarityGiulio Benetti2-19/+3
2021-01-14drm/i915/selftests: fix the uint*_t types that have crept inJani Nikula1-5/+5
2021-01-14drm/hisilicon: Fix build errorTian Tao1-1/+1
2021-01-14drm: Include <linux/mem_encrypt.h> in drm_cache.cThomas Zimmermann1-0/+1
2021-01-14drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functionsJani Nikula1-21/+16
2021-01-14drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_initJani Nikula3-5/+5
2021-01-14drm/i915/pps: add locked intel_pps_wait_power_cycleJani Nikula3-9/+14
2021-01-14drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_allJani Nikula3-6/+5
2021-01-14drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlockedJani Nikula3-3/+3
2021-01-14drm/i915/pps: abstract intel_pps_encoder_reset()Jani Nikula3-19/+25
2021-01-14drm/i915/pps: add higher level intel_pps_init() callJani Nikula3-12/+17
2021-01-14drm/i915/pps: abstract intel_pps_vdd_off_syncJani Nikula3-30/+21
2021-01-14drm/i915/pps: rename edp_panel_* to intel_pps_*_unlockedJani Nikula3-26/+26
2021-01-14drm/i915/pps: rename intel_edp_panel_* to intel_pps_*Jani Nikula4-24/+22
2021-01-14drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_*Jani Nikula3-11/+11
2021-01-14drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lockJani Nikula3-24/+25
2021-01-14drm/i915/pps: abstract panel power sequencer from intel_dp.cJani Nikula7-1343/+1397
2021-01-14drm/i915/display: fix the uint*_t types that have crept inJani Nikula4-4/+4
2021-01-14drm/i915/display: remove useless use of inlineJani Nikula1-1/+1
2021-01-14drm/i915/gt: Rearrange ivb workaroundsChris Wilson1-71/+47
2021-01-14drm/i915/gt: Rearrange vlv workaroundsChris Wilson1-44/+51
2021-01-14drm/amdgpu: add new device id for Reniormengwang2-1/+3
2021-01-14drm/amdgpu: add green_sardine device id (v2)Prike Liang1-0/+1
2021-01-14drm/amdgpu: fix vram type and bandwidth error for DDR5 and DDR4Huang Rui1-17/+36
2021-01-14drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets for VGHchen gong1-2/+14
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