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AgeCommit message (Expand)AuthorFilesLines
2018-12-11drm/nouveau/core: support multiple nvdec instancesBen Skeggs8-18/+24
2018-12-11drm/nouveau/drm/nouveau: Don't forget to label dp_aux devicesLyude Paul4-4/+12
2018-12-11drm/nouveau/drm/nouveau: Check rc from drm_dp_mst_topology_mgr_resume()Lyude Paul1-2/+10
2018-12-11drm/nouveau: Add size to vbios.rom file in debugfsLyude Paul1-4/+19
2018-12-11drm/nouveau: Add strap_peek to debugfsLyude Paul1-1/+22
2018-12-11drm/nouveau/drm/nouveau: tegra: Call nouveau_drm_device_init()Thierry Reding1-0/+6
2018-12-10drm/i915: Use intel_ types more consistently for color management code (v2)Matt Roper4-130/+117
2018-12-10drm/i915: Use intel_ types more consistently for watermark code (v2)Matt Roper4-167/+137
2018-12-10drm/dp/mst: Validate REMOTE_I2C_READ harderVille Syrjälä1-7/+18
2018-12-10drm/dp/mst: Configure no_stop_bit correctly for remote i2c xfersVille Syrjälä1-0/+1
2018-12-10drm/amdgpu/powerplay: Add special avfs cases for some polaris asics (v3)Alex Deucher1-0/+54
2018-12-10drm/amdgpu/powerplay: Apply avfs cks-off voltages on VIKenneth Feng2-0/+8
2018-12-10drm/amdgpu: update SMC firmware image for polaris10 variantsJunwei Zhang1-1/+2
2018-12-10drm/amdkfd: add new vega20 pci idAlex Deucher1-0/+1
2018-12-10drm/amdkfd: add new vega10 pci idsAlex Deucher1-0/+6
2018-12-10drm/amdgpu: add some additional vega20 pci idsAlex Deucher1-0/+1
2018-12-10drm/amdgpu: add some additional vega10 pci idsAlex Deucher1-0/+6
2018-12-10drm/amdgpu: remove set but not used variable 'grbm_soft_reset'YueHaibing1-4/+2
2018-12-10drm/amdgpu: Limit vm max ctx number to 4096Rex Zhu2-1/+2
2018-12-10drm/amdgpu: bypass RLC init under sriov for Tonga (v2)Tiecheng Zhou1-0/+5
2018-12-10drm/ast: Remove set but not used variable 'bo'YueHaibing1-2/+0
2018-12-10drm/dp-mst-helper: Remove hotplug callbackDaniel Vetter5-39/+4
2018-12-10drm/i915/gvt: remove unused parameter for hypervisor's host_exit callZhenyu Wang4-6/+5
2018-12-10drm/i915/gvt: mandatory require hypervisor's host_initZhenyu Wang1-3/+2
2018-12-08drm/vc4: Add support for X/Y reflectionBoris Brezillon1-12/+47
2018-12-08drm/vc4: Fix negative X/Y positioning on SAND planesBoris Brezillon1-0/+21
2018-12-07drm/amdgpu: move IV prescreening into the GMC codeChristian König9-154/+59
2018-12-07drm/amdgpu: remove VM fault_credit handlingChristian König7-115/+6
2018-12-07drm/amdgpu: send IVs to the KFD only after processing them v3Christian König1-21/+17
2018-12-07drm/amdkfd: Add support for doorbell BOsFelix Kuehling3-7/+62
2018-12-07drm/amdkfd: Add DMABuf import functionalityFelix Kuehling8-4/+262
2018-12-07drm/amdkfd: Add NULL-pointer checkFelix Kuehling1-1/+1
2018-12-07drm/amdgpu: Add KFD VRAM limit checkingFelix Kuehling5-54/+75
2018-12-07drm/amdgpu: Workaround build failure due to trace conflictKuehling, Felix4-1/+3
2018-12-07drm/amd/powerplay: rv dal-pplib interface refactor powerplay parthersen wu6-9/+165
2018-12-07drm/amdgpu: Skip ring soft recovery when fence was NULLwentalou1-1/+1
2018-12-07drm/amdgpu/psp: Destroy psp ring when doing gpu resetXiangliang Yu1-1/+3
2018-12-07drm/amdgpu/psp: Add support VMR ring for VFXiangliang Yu4-29/+83
2018-12-07drm/amdgpu/psp: Get psp fw version through reading registerXiangliang Yu1-1/+3
2018-12-07drm/amdgpu: always reserve one more shared slot for pipelined BO movesChristian König2-4/+6
2018-12-07drm/amdgpu: always reserve two slots for the VMChristian König2-13/+6
2018-12-07drm/amdgpu: fix using shared fence for exported BOs v2Christian König2-3/+11
2018-12-07drm/ttm: allow reserving more than one shared slot v3Christian König13-28/+33
2018-12-07drm/amdgpu: both support PCO FP5/AM4 rlc fwAaron Liu1-1/+15
2018-12-07drm/amdgpu/powerplay: check MC firmware for FFC supportAlex Deucher1-0/+8
2018-12-07drm/amdgpu/powerplay: update smu7_ppsmc.hAlex Deucher1-0/+3
2018-12-07drm/v3d: Invalidate the caches from the outside in.Eric Anholt1-2/+6
2018-12-07drm/v3d: Stop trying to flush L2C on V3D 3.3+Eric Anholt1-3/+8
2018-12-07drm/v3d: Drop the wait for L2T flush to complete.Eric Anholt1-4/+4
2018-12-07drm/v3d: Don't bother flushing L1TD at job start.Eric Anholt1-12/+0
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