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2017-12-13drm/tegra: sor: Parameterize register offsetsThierry Reding1-76/+127
Future Tegra generations have an increased number of display controllers that can drive individual SORs. In order to support that, the offset and layout of some registers has changed in backwards-incompatible ways. Use parameterized register offsets to support this. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Support ARGB and ABGR formatsThierry Reding3-0/+14
These formats can easily be supported on all generations of Tegra. Note that the XRGB and XBGR formats that we supported were in fact using the ARGB and ABGR Tegra formats. This happened to work in cases where no alpha was being considered. This change is also a fix for those formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Add Tegra186 supportThierry Reding3-81/+266
The display architecture has changed in several signifcant ways with the new Tegra186 SoC. Display controllers are a completely different design, but have been given a frontend that simulates the register interface for earlier chips. Unfortunately the frontend isn't completely backwards compatible, so the driver needs parameterization to take the changes into account. One big change is that the total number of display controllers has been increased to three. At the same time the number of planes available has remained constant. However, planes can now be freely assigned between the display controllers, giving applications more flexibility in making the best use of the available resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Add Tegra186 display hub supportThierry Reding8-3/+1103
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Move common plane code to separate fileThierry Reding4-194/+245
Subsequent patches will add support for Tegra186 which has a different architecture and needs different plane code but which can share a lot of code with earlier Tegra support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move state definition to headerThierry Reding2-18/+18
Move the display controller state definition to the header file so that it can be referenced by other files. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding1-10/+1
Both tegra_overlay_plane_funcs is identical to tegra_plane_funcs. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_overlay_plane_destroy()Thierry Reding1-6/+1
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding1-12/+3
Both tegra_primary_plane_funcs and tegra_cursor_plane_funcs are identical. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_primary_plane_destroy()Thierry Reding1-6/+1
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Remove custom page-flip handlerThierry Reding2-48/+17
Tegra display hardware has GO bits and meets all the requirements to use drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand- rolled implementation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Use atomic commit helpersThierry Reding4-107/+27
There's no reason not to use them, and they already get all the semantics right, so rip out all of the custom code and replace it by the helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Support background colorThierry Reding2-7/+15
Starting with Tegra124, the interface to set the background color (the value generated for pixels that are not sourced from any window) is via a different register. Earlier generations called this the border color. Reverse the feature flag and assume that IP revisions that don't have support for background color will support border color instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: vic: Properly align argumentsThierry Reding1-1/+1
Properly align function arguments on subsequent lines with the first argument on the first line. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Do not wrap lines unnecessarilyThierry Reding1-2/+1
The tegra_drm_alloc() function signature fits on a single line, no need to wrap it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Register debugfs in ->late_register()Thierry Reding1-34/+19
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Root debugfs files at the connectorThierry Reding1-11/+6
Rather create new files within the top-level DRM device's debugfs node, add the SOR specific files to the connector's debugfs node. This avoids the need to come up with subdirectory names and is also more intuitive. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: hdmi: Register debugfs in ->late_register()Thierry Reding1-265/+245
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dsi: Register debugfs in ->late_register()Thierry Reding1-40/+18
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Register debugfs in ->late_register()Thierry Reding2-365/+335
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Reshuffle some codeThierry Reding1-76/+76
Reshuffle some code so that functions are defined closer to where they are used. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Move register definitions into a tableThierry Reding1-119/+125
After commit 932f6529139e ("drm/tegra: sor: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: hdmi: Move register definitions into a tableThierry Reding1-169/+175
After commit 07a8aab89927 ("drm/tegra: hdmi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dsi: Move register definitions into a tableThierry Reding1-86/+82
After commit 75af8fa7fd47 ("drm/tegra: dsi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move register definitions into a tableThierry Reding1-217/+223
After commit 67e04d1ab19b ("drm/tegra: dc: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13gpu: host1x: Cleanup on initialization failureThierry Reding1-2/+9
When an error happens during the initialization of one of the sub- devices, make sure to properly cleanup all sub-devices that have been initialized up to that point. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13gpu: host1x: Rewrite conditional for better readabilityThierry Reding1-5/+7
The current check is slightly difficult to read, rewrite it to improve that a little. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Sanitize format modifiersThierry Reding1-6/+29
The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/i915: Don't check #active_requests from i915_gem_wait_for_idle()Chris Wilson2-6/+2
i915_gem_wait_for_idle() is called from inside the shrinker, to ensure that we drain the last resources from the GPU in dire circumstances (OOM). As we may allocate whilst building a request, it is then possible to hit the shrinker with a request under construction, and so we must account for the incomplete request whilst waiting. In particular, we preincrement (in reserve_engine) the i915->gt.active_requests counter and mark the GPU as busy, therefore we can not use that counter for shortcircuiting the wait-for-idle. [ 950.859024] GEM_BUG_ON(i915->gt.active_requests) [ 950.859041] WARNING: CPU: 2 PID: 2178 at drivers/gpu/drm/i915/i915_gem.c:3615 i915_gem_wait_for_idle.part.56+0x166/0x4e0 [ 950.859041] Modules linked in: ccm tun fuse nf_conntrack_netbios_ns nf_conntrack_broadcast ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 nf_conntrack_ipv6 nf_defrag_ipv6 nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack libcrc32c ebtable_nat ebtable_broute bridge stp llc ebtable_filter ebtables ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_mangle iptable_security iptable_raw arc4 iwldvm mac80211 snd_hda_codec_hdmi snd_hda_codec_idt snd_hda_codec_generic snd_hda_intel snd_hda_codec btusb snd_hda_core btrtl btbcm iwlwifi snd_hwdep btintel bluetooth snd_seq snd_seq_device snd_pcm ecdh_generic x86_pkg_temp_thermal tpm_infineon coretemp tpm_tis crc32_pclmul wmi_bmof crc32c_intel iTCO_wdt hp_wmi snd_timer iTCO_vendor_support sparse_keymap tpm_tis_core mei_me cfg80211 [ 950.859082] snd joydev tpm mei rfkill pcspkr wmi soundcore lpc_ich hp_accel lis3lv02d input_polldev binfmt_misc e1000e ptp serio_raw pps_core [ 950.859094] CPU: 2 PID: 2178 Comm: gem_exec_nop Tainted: G U 4.15.0-rc2+ #900 [ 950.859102] Hardware name: Hewlett-Packard HP ProBook 6360b/1620, BIOS 68SCF Ver. B.42 12/29/2010 [ 950.859107] task: c5119cb4 task.stack: f3ccb8d8 [ 950.859112] EIP: i915_gem_wait_for_idle.part.56+0x166/0x4e0 [ 950.859113] EFLAGS: 00010296 CPU: 2 [ 950.859114] EAX: 00000024 EBX: f36c1888 ECX: f777a044 EDX: 00000007 [ 950.859115] ESI: f36c1888 EDI: edd53958 EBP: edd53970 ESP: edd53938 [ 950.859116] DS: 007b ES: 007b FS: 00d8 GS: 0033 SS: 0068 [ 950.859117] CR0: 80050033 CR2: b7f39000 CR3: 2f2b3000 CR4: 000406d0 [ 950.859118] Call Trace: [ 950.859125] ? drm_printk+0x70/0x70 [ 950.859129] i915_gem_wait_for_idle+0x18/0x30 [ 950.859133] i915_gem_shrink+0x360/0x410 [ 950.859138] ? vmpressure+0xa8/0xf0 [ 950.859142] ? ktime_get+0x4a/0x100 [ 950.859147] i915_gem_shrink_all+0x21/0x40 [ 950.859151] i915_gem_shrinker_oom+0x23/0x130 [ 950.859156] notifier_call_chain+0x4e/0x70 [ 950.859160] __blocking_notifier_call_chain+0x2f/0x60 [ 950.859164] blocking_notifier_call_chain+0x11/0x20 [ 950.859169] out_of_memory+0x207/0x280 [ 950.859174] __alloc_pages_nodemask+0xd47/0xe60 [ 950.859179] new_slab+0x32d/0x450 [ 950.859183] ___slab_alloc.constprop.81+0x358/0x4e0 [ 950.859189] ? i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859193] ? __slab_free+0x1fe/0x310 [ 950.859197] ? native_sched_clock+0x1e/0xc0 [ 950.859201] ? i915_gem_request_alloc+0xcf/0x510 [ 950.859205] ? sched_clock+0x9/0x10 [ 950.859209] __slab_alloc.constprop.80+0x29/0x40 [ 950.859212] ? __slab_alloc.constprop.80+0x29/0x40 [ 950.859216] kmem_cache_alloc_trace+0x160/0x1a0 [ 950.859220] ? i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859224] i915_sw_fence_await_dma_fence+0x53/0x160 [ 950.859229] i915_gem_request_await_dma_fence+0x1eb/0x390 [ 950.859233] i915_gem_request_await_object+0xee/0x230 [ 950.859239] i915_gem_do_execbuffer+0xc16/0x1200 [ 950.859246] ? irqtime_account_irq+0x3e/0xc0 [ 950.859251] ? irq_exit+0x4f/0xb0 [ 950.859257] ? smp_apic_timer_interrupt+0x5f/0x110 [ 950.859261] ? apic_timer_interrupt+0x35/0x3c [ 950.859266] i915_gem_execbuffer2_ioctl+0x212/0x440 [ 950.859270] ? apic_timer_interrupt+0x35/0x3c [ 950.859274] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859279] ? insn_get_seg_base+0x1b/0x50 [ 950.859283] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859287] drm_ioctl_kernel+0x51/0xa0 [ 950.859291] drm_ioctl+0x2a3/0x350 [ 950.859294] ? i915_gem_do_execbuffer+0x1200/0x1200 [ 950.859300] ? sched_clock+0x9/0x10 [ 950.859303] ? drm_getunique+0x70/0x70 [ 950.859308] do_vfs_ioctl+0x7d/0x640 [ 950.859311] ? native_sched_clock+0x1e/0xc0 [ 950.859315] ? sched_clock+0x9/0x10 [ 950.859319] ? sched_clock_cpu+0x13/0x120 [ 950.859323] SyS_ioctl+0x4e/0x80 [ 950.859326] do_fast_syscall_32+0x75/0x250 [ 950.859331] ? irq_exit+0x4f/0xb0 [ 950.859334] entry_SYSENTER_32+0x47/0x71 [ 950.859338] EIP: 0xb7f81d11 [ 950.859339] EFLAGS: 00000296 CPU: 2 [ 950.859340] EAX: ffffffda EBX: 00000003 ECX: 40406469 EDX: bfde4c20 [ 950.859340] ESI: 00000003 EDI: 40406469 EBP: 00000003 ESP: bfde4b38 [ 950.859341] DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 007b [ 950.859343] Code: e8 30 60 01 00 83 c4 10 83 c3 04 39 f3 75 e0 8b 45 d8 8b 80 14 37 00 00 85 c0 74 13 68 dd 33 e4 c0 68 49 6f e3 c0 e8 4a 55 be ff <0f> ff 5e 5f b8 fe ff ff 3f bb 0a 00 00 00 e8 b7 14 c4 ff 8b 15 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171212132148.8124-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2017-12-13drm/i915/fence: Use rcu to defer freeing of irq_workChris Wilson1-1/+2
It is illegal to perform an immediate free of the struct irq_work from inside the irq_work callback (as irq_work_run_list modifies work->flags after execution of the work->func()). As we use the irq_work to coordinate the freeing of the callback from two different softirq paths, we need to defer the kfree from inside our irq_work callback, for which we can use kfree_rcu. Fixes: 81c0ed21aa91 ("drm/i915/fence: Avoid del_timer_sync() from inside a timer") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171213094802.28243-1-chris@chris-wilson.co.uk
2017-12-12drm/i915: Dump the engine state before declaring wedged from wait_for_engines()Chris Wilson1-1/+12
If wait_for_engines() fails and we resort to declaring the HW wedged, dump the engine state for debugging. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211194135.27095-2-chris@chris-wilson.co.uk
2017-12-12drm/i915: Bump timeout for wait_for_engines()Chris Wilson2-2/+4
Extract the timeout we use in i915_gem_idle_work_handler() and reuse it for wait_for_engines() in i915_gem_wait_for_idle(). It too has the same problem in sometimes having to wait for an extended period before the HW settles, so make use of the same timeout. References: 5427f207852d ("drm/i915: Bump wait-times for the final CS interrupt before parking") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211194135.27095-1-chris@chris-wilson.co.uk
2017-12-12drm/i915: Downgrade misleading "Memory usable" messageChris Wilson1-3/+2
It never meant what it said, as it was always the total size of the Global GTT and not a limit upon memory usage. Originally it served as a quick guide to the largest batch that could be submitted by userspace, an approximation to its maximum RSS, but was phrased badly. Today with the 48b ppgtt, it is even more meaningless. Replace with a more specific debug message; those wanting to know how much "video ram" they have should consult the userspace libraries for the relevant approximation. v2: Rebase Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171212113532.22574-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2017-12-12drm/i915: Print an error message for a reset failure on gen2Chris Wilson1-1/+4
Since on gen2, we do not universally have a GPU reset implementation, we fail i915_reset() at intel_has_gpu_reset(). However, this is also intentionally disabled for CI testing and so it only has a debug message. Promote that debug message to a user-facing error message that should explain why their machine became unusable following the GPU hang. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211204040.22858-1-chris@chris-wilson.co.uk
2017-12-12drm/amdgpu: fix MAP_QUEUES paramterMonk Liu1-1/+1
Should be 0. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/ttm: max_cpages is in unit of native pageMonk Liu1-1/+1
fix calculation. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/ttm: fix incorrect calculate on shrink_pagesMonk Liu1-0/+1
shrink_pages is in unit of Order after ttm_page_pool_free, but it is used by nr_free in next round so need change it into native page unit Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: make function names consistent in nbio filesAlex Deucher2-16/+16
All functions should have nbio_v* prefix. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: correct vce fw data and stack sizeFrank Min1-1/+1
this fix the VCE world switch hang issue Signed-off-by: Frank Min <Frank.Min@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: fix MAP_QUEUES paramterMonk Liu1-1/+1
Should be 0. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: no need with INT for fence pollingMonk Liu1-1/+1
We are polling so no need for INT. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: no need to evict VRAM in device_finiMonk Liu1-2/+1
this VRAM evict is not needed and also cost 2seconds to finish because the IRQ is software side disabled before it. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/ttm: max_cpages is in unit of native pageMonk Liu1-1/+1
fix calculation. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/ttm: fix incorrect calculate on shrink_pagesMonk Liu1-0/+1
shrink_pages is in unit of Order after ttm_page_pool_free, but it is used by nr_free in next round so need change it into native page unit Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: allow get_vm_pde to change flags as wellChristian König11-38/+54
And also provide the level for which we need a PDE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: batch PDE updates againChristian König1-109/+94
Now instead of one submission for each PDE batch them together over all PDs who need an update. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: remove keeping the addr of the VM PDsChristian König2-10/+5
No more double house keeping. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: remove last_entry_used from the VM codeChristian König2-24/+29
Not needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: avoid the modulo in amdgpu_vm_get_entryChristian König1-3/+3
We can do this with a simple mask as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: use polling mem to set SDMA3 wptr for VFPixel Ding2-8/+20
On Tonga VF, there're 2 sources updating wptr registers for sdma3: 1) polling mem and 2) doorbell. When doorbell and polling mem are both enabled on sdma3, there will be collision hit in occasion between those two sources when ucode and h/w are doing the updating on wptr register in parallel. Issue doesn't happen on CP GFX/Compute since CP drops all doorbell writes when VF is inactive. So enable polling mem and don't use doorbell for SDMA3. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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