aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2017-06-07drm/bridge: Build the panel wrapper in drm_kms_helperMaarten Lankhorst1-1/+1
2017-06-07drm/i915: Unify GT* and GT3 definitionsRodrigo Vivi1-30/+27
2017-06-07drm/i915: Remove unnecessary PORT3 definition.Rodrigo Vivi1-4/+2
2017-06-07drm/i915/cnl: Also need power well sanitize.Rodrigo Vivi1-2/+1
2017-06-07drm/i915/cnl: Add power wells for CNLVille Syrjälä2-4/+137
2017-06-07drm/i915/gen10: Set value of Indirect Context Offset for gen10Michel Thierry1-0/+5
2017-06-07drm/i915/cnl: Cannonlake has same MOCS table than Skylake.Rodrigo Vivi1-1/+1
2017-06-07drm/i915/cnl: Configure EU slice power gating.Rodrigo Vivi1-4/+3
2017-06-07drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipeJames Irwin1-1/+1
2017-06-07drm/i915/cnl: add IS_CNL_REVID macroPaulo Zanoni1-0/+6
2017-06-07drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi1-0/+1
2017-06-07drm/i915/cnl: Cannonlake uses CNP PCH.Rodrigo Vivi1-0/+4
2017-06-07drm/i915/cnl: Introduce Cannonlake platform defition.Rodrigo Vivi3-0/+12
2017-06-07drm/meson: Fix driver bind when only CVBS is availableNeil Armstrong1-5/+15
2017-06-07drm/i915: Fix 90/270 rotated coordinates for FBCVille Syrjälä1-12/+7
2017-06-07drm/i915: Restore has_fbc=1 for ILK-MVille Syrjälä1-1/+1
2017-06-07drm/i915: Workaround VLV/CHV DSI scanline counter hardware failVille Syrjälä2-0/+30
2017-06-07drm/i915: Fix logical inversion for gen4 quirkingChris Wilson1-1/+1
2017-06-07drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionallyChris Wilson1-1/+2
2017-06-07drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.Maarten Lankhorst1-0/+9
2017-06-07drm/i915: Prevent the system suspend complete optimizationImre Deak1-0/+9
2017-06-07drm/i915/psr: disable psr2 for resolution greater than 32X20Nagaraju, Vathsala1-2/+3
2017-06-07drm/i915: Hold a wakeref for probing the ring registersChris Wilson1-1/+17
2017-06-07drm/i915: Short-circuit i915_gem_wait_for_idle() if already idleChris Wilson1-0/+4
2017-06-07drm/i915: Disable decoupled MMIOKai Chen1-1/+0
2017-06-07drm/i915/guc: Remove stale comment for q_failMichal Wajdeczko1-2/+0
2017-06-07drm/vmwgfx: Bump driver minor and dateThomas Hellstrom1-2/+2
2017-06-07drm/vmwgfx: Remove unused legacy cursor functionsSinclair Yeh2-129/+0
2017-06-07drm/vmwgfx: fix spelling mistake "exeeds" -> "exceeds"Colin Ian King1-1/+1
2017-06-07drm/vmwgfx: Fix large topology crashSinclair Yeh1-5/+17
2017-06-07ACPI: Switch to use generic guid_t in acpi_evaluate_dsm()Andy Shevchenko3-25/+18
2017-06-07drm/vmwgfx: Make sure to update STDU when FB is updatedSinclair Yeh1-0/+5
2017-06-07drm/vmwgfx: Make sure backup_handle is always validSinclair Yeh1-7/+11
2017-06-07drm/vmwgfx: Handle vmalloc() failure in vmw_local_fifo_reserve()Dan Carpenter1-0/+2
2017-06-07drm/vmwgfx: Don't create proxy surface for cursorSinclair Yeh1-0/+1
2017-06-07drm/vmwgfx: limit the number of mip levels in vmw_gb_surface_define_ioctl()Vladis Dronov1-0/+3
2017-06-07drm/i915: Serialize GTT/Aperture accesses on BXTJon Bloomfield2-0/+113
2017-06-07drm/amdgpu/gfx: create a common bitmask function (v2)Alex Deucher5-40/+25
2017-06-07drm/amdgpu/gfx8: drop per-APU CU limitsAlex Deucher1-69/+2
2017-06-06drm/amdgpu/gfx6: properly cache mc_arb_ramcfgAlex Deucher1-1/+2
2017-06-06drm/amdgpu/gfx9: new queue policy, take first 2 queues of each pipeAlex Deucher1-2/+2
2017-06-06drm/amdgpu/gfx9: allocate queues horizontally across pipesAlex Deucher1-61/+50
2017-06-06drm/amd/powerplay: fix memory leak in cz_hwmgr backendHawking Zhang1-0/+6
2017-06-06drm/amd/powerplay: fix memory leak in rv_hwmgr backendHawking Zhang1-0/+10
2017-06-06drm/amd/powerplay: add sclk and mclk overdrive for vega10Eric Huang1-15/+133
2017-06-06drm/amd/powerplay: fix populate dpm level failed when s3 on vega10.Rex Zhu1-7/+6
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gmc9Huang Rui1-5/+5
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for mmhubHuang Rui1-90/+79
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gfxhubHuang Rui1-73/+60
2017-06-06drm/amdgpu: fix the gart table cleared issue for S3Huang Rui6-1/+14
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.