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path: root/drivers/irqchip/irq-sifive-plic.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-06-10irqchip: Bulk conversion to generic_handle_domain_irq()Marc Zyngier1-5/+3
2021-04-07irqchip/sifive-plic: Mark two global variables __ro_after_initJisheng Zhang1-2/+2
2020-11-01irqchip/sifive-plic: Fix chip_data access within a hierarchyGreentime Hu1-4/+4
2020-10-25irqchip/sifive-plic: Fix broken irq_set_affinity() callbackGreentime Hu1-1/+1
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverAnup Patel1-9/+23
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel1-15/+1
2020-05-25irqchip/sifive-plic: Improve boot prints for multiple PLIC instancesAnup Patel1-2/+2
2020-05-25irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is presentAnup Patel1-2/+12
2020-05-25irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()Anup Patel1-0/+3
2020-05-18irqchip/sifive-plic: Remove incorrect requirement about number of irq contextsWesley W. Terpstra1-2/+0
2020-04-17irqchip/sifive-plic: Fix maximum priority threshold valueAtish Patra1-1/+1
2020-03-16irqchip/sifive-plic: Add support for multiple PLICsAtish Patra1-30/+51
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra1-4/+34
2020-01-24Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/coreThomas Gleixner1-4/+26
2020-01-20irqchip/sifive-plic: Support irq domain hierarchyYash Shah1-4/+26
2020-01-04riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley1-1/+1
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-4/+7
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner1-2/+2
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak1-2/+2
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner1-14/+15
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier1-14/+15
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig1-2/+10
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostAnup Patel1-6/+39
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextAnup Patel1-8/+8
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentAnup Patel1-0/+5
2019-02-21irqchip/sifive-plic: Pre-compute context hart base and enable baseAnup Patel1-26/+21
2019-02-14irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Atish Patra1-0/+5
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-3/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt1-1/+1
2018-08-13irqchip: add a SiFive PLIC driverChristoph Hellwig1-0/+260
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