Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-02-21 | irqchip/sifive-plic: Implement irq_set_affinity() for SMP host | 1 | -6/+39 | |
2019-02-21 | irqchip/sifive-plic: Differentiate between PLIC handler and context | 1 | -8/+8 | |
2019-02-21 | irqchip/sifive-plic: Add warning in plic_init() if handler already present | 1 | -0/+5 | |
2019-02-21 | irqchip/sifive-plic: Pre-compute context hart base and enable base | 1 | -26/+21 | |
2019-02-14 | irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid. | 1 | -0/+5 | |
2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | 1 | -3/+5 | |
2018-10-22 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | 1 | -1/+1 | |
2018-08-13 | irqchip: add a SiFive PLIC driver | 1 | -0/+260 |