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path: root/drivers/irqchip/irq-sifive-plic.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-4/+7
2019-10-25Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner1-2/+2
2019-10-25irqchip/sifive-plic: Skip contexts except supervisor in plic_init()Alan Mikhak1-2/+2
2019-10-14Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner1-14/+15
2019-09-18irqchip/sifive-plic: Switch to fasteoi flowMarc Zyngier1-14/+15
2019-09-05irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig1-2/+10
2019-02-21irqchip/sifive-plic: Implement irq_set_affinity() for SMP hostAnup Patel1-6/+39
2019-02-21irqchip/sifive-plic: Differentiate between PLIC handler and contextAnup Patel1-8/+8
2019-02-21irqchip/sifive-plic: Add warning in plic_init() if handler already presentAnup Patel1-0/+5
2019-02-21irqchip/sifive-plic: Pre-compute context hart base and enable baseAnup Patel1-26/+21
2019-02-14irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.Atish Patra1-0/+5
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-3/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt1-1/+1
2018-08-13irqchip: add a SiFive PLIC driverChristoph Hellwig1-0/+260