aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/media/i2c
AgeCommit message (Expand)AuthorFilesLines
2021-01-12media: ov5647: Rationalize driver structure nameJacopo Mondi1-23/+23
2021-01-12media: ov5647: Support gain, exposure and AWB controlsDavid Plowman1-2/+170
2021-01-12media: ov5647: Protect s_stream() with mutexJacopo Mondi1-2/+9
2021-01-12media: ov5647: Implement enum_frame_size()Jacopo Mondi1-3/+22
2021-01-12media: ov5647: Program mode at s_stream(1) timeJacopo Mondi1-37/+44
2021-01-12media: ov5647: Fix return value from read/writeJacopo Mondi1-4/+8
2021-01-12media: ov5647: Replace license with SPDX identifierJacopo Mondi1-9/+1
2021-01-12media: ov5647: Fix style issuesJacopo Mondi1-55/+47
2021-01-12media: ov5647: Fix format initializationJacopo Mondi1-3/+2
2021-01-12media: ov5647: Add set_fmt and get_fmt calls.Dave Stevenson1-0/+19
2021-01-12media: ov5647: Add support for non-continuous clock modeDave Stevenson1-4/+20
2021-01-12media: ov5647: Add support for PWDN GPIO.Dave Stevenson1-0/+32
2021-01-12media: i2c: imx219: take lock in imx219_enum_mbus_code/frame_sizeHans Verkuil1-1/+7
2021-01-07media: ccs: Get static data version minor correctlySakari Ailus1-1/+1
2021-01-07media: ccs-pll: Fix link frequency for C-PHYSakari Ailus1-7/+1
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwareSakari Ailus1-0/+4
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus1-0/+5
2020-12-07media: ccs: Print written register valuesSakari Ailus1-0/+4
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus1-1/+8
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus2-20/+46
2020-12-07media: ccs: Dual PLL supportSakari Ailus2-3/+51
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus2-22/+196
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus1-27/+37
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus1-5/+7
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus1-26/+25
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus2-57/+95
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus1-18/+65
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus1-23/+31
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus3-29/+64
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus1-124/+131
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus1-9/+26
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus1-0/+9
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus3-8/+23
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus3-6/+16
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus3-1/+7
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus4-19/+23
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus1-1/+10
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus2-11/+31
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus1-2/+2
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus1-2/+1
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus1-2/+9
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus1-8/+4
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus1-2/+5
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus1-0/+89
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus3-3/+4
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus2-15/+4
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus1-2/+8
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.