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AgeCommit message (Expand)AuthorFilesLines
2019-07-12Merge branch 'pci/trivial'Bjorn Helgaas6-6/+6
2019-07-12Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas1-6/+5
2019-07-12Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-82/+507
2019-07-12Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-61/+54
2019-07-12Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas1-213/+312
2019-07-12Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas1-6/+9
2019-07-12Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas5-35/+80
2019-07-12Merge branch 'remotes/lorenzo/pci/armada'Bjorn Helgaas1-1/+81
2019-07-09PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIBYueHaibing1-0/+1
2019-07-09PCI: Fix typos and whitespace errorsBjorn Helgaas6-6/+6
2019-07-08PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr()Hou Zhiqiang1-3/+2
2019-07-08PCI: mobiveil: Fix infinite-loop in the INTx handling functionHou Zhiqiang1-3/+9
2019-07-08PCI: mobiveil: Move PCIe PIO enablement out of inbound window routineHou Zhiqiang1-4/+5
2019-07-08PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound windowHou Zhiqiang1-3/+6
2019-07-08PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound windowHou Zhiqiang1-1/+4
2019-07-08PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setupHou Zhiqiang1-2/+2
2019-07-08PCI: mobiveil: Clear the control fields before updating itHou Zhiqiang1-5/+12
2019-07-08PCI: mobiveil: Add configured inbound windows counterHou Zhiqiang1-0/+1
2019-07-08PCI: mobiveil: Fix the valid check for inbound and outbound windowsHou Zhiqiang1-2/+2
2019-07-08PCI: mobiveil: Clean-up program_{ib/ob}_windows()Hou Zhiqiang1-17/+8
2019-07-08PCI: mobiveil: Remove an unnecessary return value checkHou Zhiqiang1-2/+0
2019-07-08PCI: mobiveil: Fix error return valuesHou Zhiqiang1-3/+3
2019-07-08PCI: mobiveil: Refactor the MEM/IO outbound window initializationHou Zhiqiang1-10/+10
2019-07-08PCI: mobiveil: Make some register updates more readableHou Zhiqiang1-18/+25
2019-07-08PCI: mobiveil: Reformat the code for readabilityHou Zhiqiang1-101/+107
2019-07-08PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device()Hou Zhiqiang1-1/+1
2019-07-08PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbersHou Zhiqiang1-0/+6
2019-07-08PCI: mobiveil: Move IRQ chained handler setup out of DT parseHou Zhiqiang1-2/+2
2019-07-08PCI: mobiveil: Move the link up waiting out of mobiveil_host_init()Hou Zhiqiang1-8/+7
2019-07-08PCI: mobiveil: Fix the Class Code fieldHou Zhiqiang1-3/+6
2019-07-08PCI: mobiveil: Use the 1st inbound window for MEM inbound transactionsHou Zhiqiang1-1/+1
2019-07-08PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound windowHou Zhiqiang1-3/+2
2019-07-08PCI: mobiveil: Update the resource list traversal functionHou Zhiqiang1-2/+2
2019-07-08PCI: mobiveil: Fix PCI base address in MEM/IO outbound windowsHou Zhiqiang1-2/+3
2019-07-08PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSIHou Zhiqiang1-1/+1
2019-07-08PCI: mobiveil: Unify register accessorsHou Zhiqiang1-55/+124
2019-07-05PCI: imx6: Simplify Kconfig depends onLeonard Crestez1-1/+1
2019-07-05PCI: hv: Fix a use-after-free bug in hv_eject_device_work()Dexuan Cui1-6/+9
2019-07-05PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30Vidya Sagar1-2/+5
2019-07-05PCI: tegra: Change link retry log level to debugManikanta Maddireddy1-1/+1
2019-07-05PCI: tegra: Add support for GPIO based PERST#Manikanta Maddireddy1-6/+43
2019-06-27PCI: dwc: Export APIs to support .remove() implementationVidya Sagar2-0/+8
2019-06-27PCI: dwc: Cleanup DBI,ATU read and write APIsVidya Sagar2-34/+57
2019-06-27PCI: dwc: Add API support to de-initialize hostVidya Sagar2-0/+13
2019-06-26PCI: xilinx-nwl: Fix Multi MSI data programmingBharat Kumar Gogada1-6/+5
2019-06-20PCI: tegra: Put PEX CLK & BIAS pads in DPD modeManikanta Maddireddy1-1/+12
2019-06-20PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC structManikanta Maddireddy1-2/+5
2019-06-20PCI: tegra: Change PRSNT_SENSE IRQ log to debugManikanta Maddireddy1-1/+1
2019-06-20PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20Manikanta Maddireddy1-5/+13
2019-06-20PCI: tegra: Fix PLLE power down issue due to CLKREQ# signalManikanta Maddireddy1-1/+12
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