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path: root/drivers/soc/xilinx/xlnx_vcu.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-02-08clk: xilinx: move xlnx_vcu clock driver from socMichael Tretter1-743/+0
2021-02-08soc: xilinx: vcu: fix alignment to open parenthesisMichael Tretter1-1/+1
2021-02-08soc: xilinx: vcu: fix repeated word the in commentMichael Tretter1-1/+1
2021-02-08soc: xilinx: vcu: use bitfields for register definitionMichael Tretter1-81/+34
2021-02-08soc: xilinx: vcu: remove calculation of PLL configurationMichael Tretter1-117/+0
2021-02-08soc: xilinx: vcu: make the PLL configurableMichael Tretter1-37/+103
2021-02-08soc: xilinx: vcu: make pll post divider explicitMichael Tretter1-16/+36
2021-02-08soc: xilinx: vcu: implement clock provider for output clocksMichael Tretter1-37/+160
2021-02-08soc: xilinx: vcu: register PLL as fixed rate clockMichael Tretter1-1/+18
2021-02-08soc: xilinx: vcu: implement PLL disableMichael Tretter1-9/+19
2021-02-08soc: xilinx: vcu: add helpers for configuring PLLMichael Tretter1-67/+104
2021-02-08soc: xilinx: vcu: add helper to wait for PLL lockedMichael Tretter1-19/+27
2021-02-08soc: xilinx: vcu: drop coreclk from struct xlnx_vcuMichael Tretter1-4/+2
2020-12-09soc: xilinx: vcu: use vcu-settings syscon registersMichael Tretter1-47/+47
2020-12-09soc: xilinx: vcu: drop useless success messageMichael Tretter1-2/+0
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig1-2/+2
2018-01-16soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdivGustavo A. R. Silva1-1/+1
2018-01-08soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driverDhaval Shah1-0/+630