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2014-10-24drm/i915: Merge of visible and !visible paths for primary planesGustavo Padovan1-55/+92
2014-10-24drm/i915: Remove IS_ULT()Damien Lespiau1-1/+0
2014-10-24drm/i915/skl: Don't check for ULT/ULX when detecting the PCHDamien Lespiau1-2/+0
2014-10-24drm/i915: Use IS_HSW_ULT() in HSW CDCLK clock read-outDamien Lespiau1-1/+1
2014-10-24drm/i915: Spell out IS_HSW/BDW_ULT() in intel_crt_present()Damien Lespiau1-1/+1
2014-10-24drm/i915: Use IS_HSW_ULT() in HAS_IPS()Damien Lespiau1-1/+1
2014-10-24drm/i915: Use IS_HSW_ULT() in a HSW specific code pathDamien Lespiau1-2/+2
2014-10-24drm/i915: kerneldoc for intel_fifo_underrun.cDaniel Vetter1-17/+65
2014-10-24drm/i915: Filter gmch fifo underruns in the shared handlerDaniel Vetter3-7/+11
2014-10-24drm/i915: Add wrappers to handle fifo underrun interruptsDaniel Vetter3-51/+42
2014-10-24drm/i915: Use dev_priv in public intel_fifo_underrun.c functionsDaniel Vetter4-45/+58
2014-10-24drm/i915: Extract intel_fifo_underrun.cDaniel Vetter5-294/+334
2014-10-24Revert "drm/i915: Enable full PPGTT on gen7"Daniel Vetter1-1/+1
2014-10-21Merge branch 'drm-intel-next-fixes' into drm-intel-nextDaniel Vetter9-298/+116
2014-10-16drm/i915: fix short vs. long hpd detectionJani Nikula1-7/+7
2014-10-16drm/i915: Don't trust the DP_DETECT bit for eDP ports on CHVVille Syrjälä1-12/+21
2014-10-08drm/i915: properly reenable gen8 pipe IRQsPaulo Zanoni1-2/+3
2014-10-06drm/i915: Move DIV_ROUND_CLOSEST_ULL macro to headerU. Artie Eoff3-6/+3
2014-10-06drm/i915: intel_backlight scale() math WAU. Artie Eoff1-3/+5
2014-10-03drm/i915: Update DRIVER_DATE to 20141003Daniel Vetter1-1/+1
2014-10-03drm/i915: Remove the duplicated logic between the two shrink phasesChris Wilson1-30/+19
2014-10-03drm/i915: kerneldoc for interrupt enable/disable functionsDaniel Vetter1-2/+59
2014-10-03drm/i915: Use dev_priv instead of dev in irq setup functionsDaniel Vetter6-35/+31
2014-10-03drm/i915: s/pm._irqs_disabled/pm.irqs_enabled/Daniel Vetter6-19/+27
2014-10-03drm/i915: Clear TX FIFO reset master override bits on chvVille Syrjälä3-0/+30
2014-10-03drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chvVille Syrjälä3-0/+47
2014-10-02drm/i915: make sink_crc return -EIO on aux read/write failureRodrigo Vivi1-6/+13
2014-10-02drm/i915: Constify send buffer for intel_dp_aux_chDaniel Vetter1-1/+1
2014-10-02drm/i915: De-magic the PSR AUX messageVille Syrjälä2-7/+16
2014-10-01drm/i915: Reinstate error level message for non-simulated gpu hangsDaniel Vetter1-0/+3
2014-10-01drm/i915: Kerneldoc for intel_runtime_pm.cDaniel Vetter1-1/+165
2014-10-01drm/i915: Call runtime_pm_disable directlyDaniel Vetter3-20/+19
2014-10-01drm/i915: Move intel_display_set_init_power to intel_runtime_pm.cDaniel Vetter3-15/+16
2014-10-01drm/i915: Bikeshed rpm functions name a bit.Daniel Vetter13-50/+51
2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter4-1179/+1214
2014-10-01drm/i915: Remove intel_modeset_suspend_hwDaniel Vetter3-7/+1
2014-10-01drm/i915: spelling fixes for frontbuffer tracking kerneldocDaniel Vetter2-8/+7
2014-10-01drm/i915: Tighting frontbuffer tracking around flipsDaniel Vetter1-2/+3
2014-10-01drm/i915: Enable pixel replicated modes on BDW and HSW.Clint Taylor2-1/+14
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter76-699/+1216
2014-09-30drm/i915: preserve other DP_TEST_SINK bits.Rodrigo Vivi1-2/+6
2014-09-30drm/i915/bdw: WaDisableFenceDestinationToSLMRodrigo Vivi2-1/+6
2014-09-30drm/i915: Add IS_BDW_GT3 macro.Rodrigo Vivi1-0/+2
2014-09-30drm/i915: Fix Sink CRCRodrigo Vivi1-6/+17
2014-09-29drm/i915: Don't spam dmesg with rps messages on vlv/chvVille Syrjälä1-6/+7
2014-09-29drm/i915: Do not leak pages when freeing userptr objectsTvrtko Ursulin1-4/+3
2014-09-29drm/i915: Do not store the error pointer for a failed userptr registrationChris Wilson1-8/+16
2014-09-29Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter5-239/+37
2014-09-29drm/i915: Broadwell DDI Buffer translation - more tuningRodrigo Vivi1-1/+1
2014-09-29drm/i915: Broadwell DDI Buffer translation changed to give better margin.Rodrigo Vivi1-2/+2
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