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2021-11-11drm/i915/fbc: Start passing around intel_fbcVille Syrjälä7-208/+200
2021-11-11drm/i915/fbc: s/dev_priv/i915/Ville Syrjälä1-263/+263
2021-11-11drm/i915: Relocate FBC_LLC_READ_CTRLVille Syrjälä1-3/+3
2021-11-11drm/i915/fbc: Finish polishing FBC1 registersVille Syrjälä2-27/+37
2021-11-11drm/i915/fbc: Clean up all register definesVille Syrjälä3-61/+62
2021-11-11drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASKVille Syrjälä2-6/+2
2021-11-11drm/i915/fbc: Introduce intel_fbc_set_false_color()Ville Syrjälä3-17/+30
2021-11-11drm/i915/fbc: Introduce .program_cfb() vfuncVille Syrjälä1-19/+37
2021-11-11drm/i915/fbc: s/gen7/ivb/Ville Syrjälä1-8/+8
2021-11-11drm/i915/fbc: Introduce .nuke() vfuncVille Syrjälä1-61/+84
2021-11-11drm/i915/fbc: Introduce intel_fbc_funcsVille Syrjälä2-28/+55
2021-11-11drm/i915/fbc: Extract helpers to compute FBC control register valuesVille Syrjälä1-61/+87
2021-11-11drm/i915/fbc: Introduce intel_fbc_is_compressing()Ville Syrjälä3-19/+41
2021-11-11drm/i915/fbc: Just use params->fence_y_offset alwaysVille Syrjälä1-6/+4
2021-11-11drm/i915/fbc: Extract {skl,glk}_fbc_program_cfb_stride()Ville Syrjälä1-19/+32
2021-11-11drm/i915/fbc: Extract snb_fbc_program_fence()Ville Syrjälä1-20/+19
2021-11-11drm/i915/dsi: transmit brightness command in HS stateWilliam Tseng1-0/+4
2021-11-11drm/i915/dp: For PCON TMDS mode set only the relavant bits in config DPCDAnkit Nautiyal1-1/+23
2021-11-11drm/i915/dp: Optimize the FRL configuration for HDMI2.1 PCONAnkit Nautiyal1-14/+23
2021-11-10Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping"Vandita Kulkarni1-8/+2
2021-11-09drm/i915: pin: delete duplicate check in intel_pin_and_fence_fb_obj()Dan Carpenter1-7/+5
2021-11-10drm/i915: Call intel_update_active_dpll() for both bigjoiner pipesVille Syrjälä1-1/+7
2021-11-10drm/i915: Use unlocked register accesses for LUT loadsVille Syrjälä2-66/+66
2021-11-10drm/i915: Use vblank workers for gamma updatesVille Syrjälä5-10/+129
2021-11-10drm/i915: Do vrr push before sampling the frame counterVille Syrjälä1-3/+3
2021-11-09drm/i915/dsi: disable lpdt if it is not enabledWilliam Tseng1-0/+2
2021-11-08drm/i915: Fix Memory BW formulae for ADL-PRadhakrishna Sripada1-1/+1
2021-11-05drm/i915/display/adlp: Disable underrun recoveryJosé Roberto de Souza1-32/+7
2021-11-05drm/i915/audio: rename intel_init_audio_hooks to intel_audio_hooks_initJani Nikula3-4/+4
2021-11-05drm/i915/audio: move intel_audio_funcs internal to intel_audio.cJani Nikula2-9/+10
2021-11-05drm/i915/audio: define the audio struct separately from drm_i915_privateJani Nikula1-21/+24
2021-11-05drm/i915/audio: name the audio sub-struct in drm_i915_privateJani Nikula4-79/+77
2021-11-05drm/i915/audio: group audio under anonymous struct in drm_i915_privateJani Nikula1-21/+22
2021-11-04drm/i915: Update memory bandwidth formulaeRadhakrishna Sripada1-32/+179
2021-11-04drm/i915: Split vlv/chv sprite plane update into noarm+arm pairVille Syrjälä1-15/+30
2021-11-04drm/i915: Split ivb+ sprite plane update into noarm+arm pairVille Syrjälä1-14/+28
2021-11-04drm/i915: Split g4x+ sprite plane update into noarm+arm pairVille Syrjälä1-13/+28
2021-11-04drm/i915: Split pre-skl primary plane update into noarm+arm pairVille Syrjälä1-22/+59
2021-11-04drm/i915: Split skl+ plane update into noarm+arm pairVille Syrjälä1-41/+72
2021-11-04drm/i915: Split update_plane() into update_noarm() + update_arm()Ville Syrjälä9-94/+192
2021-11-04drm/i915: Fix up the sprite namespacingVille Syrjälä1-53/+53
2021-11-04drm/i915: Fix async flip with decryption and/or DPTVille Syrjälä1-10/+20
2021-11-04drm/i915: Reject planar formats when doing async flipsVille Syrjälä1-0/+6
2021-11-03drm/i915: Use intel_de_rmw() for icl combo phy programmingVille Syrjälä1-26/+18
2021-11-03drm/i915: Use intel_de_rmw() for icl mg phy programmingVille Syrjälä1-73/+42
2021-11-03drm/i915: Use intel_de_rmw() for tgl dkl phy programmingVille Syrjälä1-21/+17
2021-11-03drm/i915: Enable per-lane drive settings for icl+Ville Syrjälä1-1/+4
2021-11-03drm/i915: Query the vswing levels per-lane for snps phyVille Syrjälä1-1/+1
2021-11-03drm/i915: Query the vswing levels per-lane for tgl dkl phyVille Syrjälä1-14/+19
2021-11-03drm/i915: Query the vswing levels per-lane for icl mg phyVille Syrjälä1-1/+12
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