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2014-10-01drm/i915: Kerneldoc for intel_runtime_pm.cDaniel Vetter1-1/+165
2014-10-01drm/i915: Call runtime_pm_disable directlyDaniel Vetter3-20/+19
2014-10-01drm/i915: Move intel_display_set_init_power to intel_runtime_pm.cDaniel Vetter3-15/+16
2014-10-01drm/i915: Bikeshed rpm functions name a bit.Daniel Vetter13-50/+51
2014-10-01drm/i915: Extract intel_runtime_pm.cDaniel Vetter4-1179/+1214
2014-10-01drm/i915: Remove intel_modeset_suspend_hwDaniel Vetter3-7/+1
2014-10-01drm/i915: spelling fixes for frontbuffer tracking kerneldocDaniel Vetter2-8/+7
2014-10-01drm/i915: Tighting frontbuffer tracking around flipsDaniel Vetter1-2/+3
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter76-699/+1216
2014-09-30drm/i915: preserve other DP_TEST_SINK bits.Rodrigo Vivi1-2/+6
2014-09-30drm/i915/bdw: WaDisableFenceDestinationToSLMRodrigo Vivi2-1/+6
2014-09-30drm/i915: Add IS_BDW_GT3 macro.Rodrigo Vivi1-0/+2
2014-09-30drm/i915: Fix Sink CRCRodrigo Vivi1-6/+17
2014-09-29drm/i915: Broadwell DDI Buffer translation - more tuningRodrigo Vivi1-1/+1
2014-09-29drm/i915: Broadwell DDI Buffer translation changed to give better margin.Rodrigo Vivi1-2/+2
2014-09-29drm/i915: Make sure PSR is ready for been re-enabled.Rodrigo Vivi1-0/+11
2014-09-29drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi4-6/+21
2014-09-24drm/i915: Avoid re-configure panel on every PSR re-enable.Rodrigo Vivi1-4/+4
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau1-3/+3
2014-09-24drm/i915/skl: Introduce intel_num_planes()Damien Lespiau1-0/+8
2014-09-24drm/i915/skl: Introduce a I915_MAX_PLANES macroDamien Lespiau1-0/+8
2014-09-24drm/i915/skl: Adjust assert_sprites_disabled()Damien Lespiau1-1/+8
2014-09-24drm/i915/skl: Implement drm_plane vfuncsDamien Lespiau2-1/+234
2014-09-24drm/i915/skl: Skylake has 2 "sprite" planes per pipeDamien Lespiau1-1/+1
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau2-0/+11
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau1-0/+4
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau1-0/+8
2014-09-24drm/i915/skl: Sunrise Point PCH detectionSatheeshakrishna M2-0/+14
2014-09-24drm/i915/skl: Adjust the display engine interruptsDamien Lespiau2-9/+41
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M1-1/+1
2014-09-24drm/i915/skl: SKL backlight enablingSatheeshakrishna M1-1/+1
2014-09-24drm/i915/skl: vfuncs for skl eld and global resourceSatheeshakrishna M1-0/+4
2014-09-24drm/i915/skl: SKL pipe misc programmingSatheeshakrishna M1-1/+1
2014-09-24drm/i915/skl: SKL shares the same underrun interrupt as BDWDamien Lespiau1-1/+1
2014-09-24drm/i915/skl: Report the PDP regs as in gen8Damien Lespiau1-0/+1
2014-09-24drm/i915/skl: report the same INSTDONE registers as gen8Damien Lespiau1-0/+1
2014-09-24drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMPDamien Lespiau1-1/+1
2014-09-24drm/i915/skl: Initialize PPGTT like gen8Damien Lespiau1-1/+1
2014-09-24drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylakeDamien Lespiau2-1/+20
2014-09-24drm/i915/skl: Implement the get_aux_clock_divider() DP vfuncDamien Lespiau1-1/+13
2014-09-24drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+Damien Lespiau1-0/+1
2014-09-24drm/i915/skl: Add the additional graphics stolen sizesDamien Lespiau1-1/+16
2014-09-24drm/i915/skl: Skylake moves AUX_CTL from PCH to CPUDamien Lespiau1-1/+10
2014-09-24drm/i915/skl: Add support for DP voltage swings and pre-emphasisDamien Lespiau1-3/+16
2014-09-24drm/i915/skl: Program the DDI buffer translation tablesDamien Lespiau1-2/+38
2014-09-24drm/i915/skl: Don't try to read out the PCH transcoder state if not presentDamien Lespiau1-1/+2
2014-09-24drm/i915/skl: Don't create a VGA connector on SkylakeDamien Lespiau1-0/+3
2014-09-24drm/i915/skl: Implement the new update_plane() for primary planesDamien Lespiau2-3/+199
2014-09-24drm/i915/skl: i915_swizzle_info gen9 fixRobert Beckett1-1/+1
2014-09-24drm/i915/skl: Framebuffers need to be aligned to 256KB on SkylakeDamien Lespiau1-3/+9
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