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2015-11-18drm/i915: Type safe register read/writeVille Syrjälä35-1564/+1531
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä1-1/+1
2015-11-18drm/i915: Add 'offset' to uncore funcsVille Syrjälä1-23/+25
2015-11-18drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+Ville Syrjälä1-26/+54
2015-11-18drm/i915: Turn vgpu pdps into an arrayVille Syrjälä2-15/+8
2015-11-18drm/i915: Wrap context LRI init in a macroVille Syrjälä1-51/+40
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä2-11/+19
2015-11-18drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä1-4/+4
2015-11-18drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä1-4/+6
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä10-23/+33
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä2-14/+35
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä2-12/+16
2015-11-18drm/i915: s/0x50/RING_PSMI_CTL/Ville Syrjälä1-1/+1
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä2-31/+40
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä3-9/+6
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä1-130/+130
2015-11-18drm/i915: Streamline gpio_mmio_base deductionVille Syrjälä1-8/+7
2015-11-18drm/i915: Store DVO SRCDIM register offset under intel_dvo_deviceVille Syrjälä2-14/+10
2015-11-18drm/i915: s/is_sdvob/enum port/Ville Syrjälä3-23/+32
2015-11-18drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only userVille Syrjälä3-23/+19
2015-11-18pci: Decouple quirks.c from i915_reg.hVille Syrjälä1-1/+3
2015-11-18drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_priv.Rodrigo Vivi2-13/+6
2015-11-18drm/i915: Stop tracking last calculated Sink CRC.Rodrigo Vivi2-32/+9
2015-11-18drm/i915: Make Sink crc calculation waiting for counter to reset.Rodrigo Vivi1-1/+18
2015-11-18drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.Rodrigo Vivi1-0/+4
2015-11-17drm/i915/skl: Remove unused suspend and resume callbacksPatrik Jakobsson1-17/+0
2015-11-17drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson3-3/+18
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson4-35/+90
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson1-0/+4
2015-11-17drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson1-3/+0
2015-11-17drm/i915: Add a modeset power domainPatrik Jakobsson2-0/+3
2015-11-17drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson4-78/+45
2015-11-17drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä1-5/+1
2015-11-17drm/i915: Introduce a gmbus power domainVille Syrjälä6-40/+13
2015-11-17drm/i915: Clean up AUX power domain handlingVille Syrjälä3-34/+59
2015-11-17drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson1-18/+17
2015-11-17drm/i915: Don't trust CSR program memory contentsPatrik Jakobsson1-7/+3
2015-11-17drm/i915: fix handling of the disable_power_well module optionImre Deak2-2/+16
2015-11-17drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak1-5/+0
2015-11-17drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLKImre Deak1-10/+4
2015-11-17drm/i915/skl: disable DC states before display core init/uninitImre Deak1-0/+4
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak2-36/+28
2015-11-17drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak1-27/+9
2015-11-17drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak5-21/+61
2015-11-17drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak1-2/+2
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau4-4/+35
2015-11-17drm/i915: fix lookup_power_well for power wells without any domainImre Deak1-2/+4
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak2-1/+5
2015-11-17drm/i915: get runtime PM reference around GEM set_tiling IOCTLImre Deak1-0/+4
2015-11-17drm/i915: Serialise updates to GGTT with access through GGTT on BraswellChris Wilson2-0/+25
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