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2022-09-08drm/i915: Round TMDS clock to nearestVille Syrjälä2-2/+3
2022-09-08drm/i915: Use a fixed N value alwaysVille Syrjälä5-29/+24
2022-09-08drm/i915: Allow M/N change during fastset on bdw+Ville Syrjälä3-8/+43
2022-09-08drm/i915: Add intel_panel_highest_mode()Ville Syrjälä2-0/+18
2022-09-08drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabledVille Syrjälä1-3/+5
2022-09-08drm/i915: Nuke fastet state copy hacksVille Syrjälä1-25/+3
2022-09-08drm/i915: Set active dpll early for icl+Ville Syrjälä1-0/+6
2022-09-08drm/i915: Make all clock checks non-fuzzyVille Syrjälä1-15/+4
2022-09-08drm/i915: Make M/N checks non-fuzzyVille Syrjälä2-45/+13
2022-09-08drm/i915: Compute clocks earlierVille Syrjälä1-4/+4
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä7-12/+117
2022-09-08drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()Ville Syrjälä2-20/+3
2022-09-08drm/i915: Do .crtc_compute_clock() earlierVille Syrjälä2-7/+5
2022-09-07drm/i915/vdsc: Set VDSC PIC_HEIGHT before using for DP DSCAnkit Nautiyal3-1/+3
2022-09-07drm/i915/dsi: Extract {vlv,bxt}_get_pclk()Ville Syrjälä1-53/+68
2022-09-07drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()Ville Syrjälä3-3/+4
2022-09-07drm/i915: Shuffle some PLL code aroundVille Syrjälä1-85/+85
2022-09-07drm/i915: Relocate intel_crtc_dotclock()Ville Syrjälä2-22/+22
2022-09-06Revert "drm/i915: Fix intel_dp_mst_compute_link_config"Jani Nikula1-14/+2
2022-09-06Revert "drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function"Jani Nikula1-41/+13
2022-09-06Revert "drm/i915: Add DSC support to MST path"Jani Nikula3-174/+42
2022-09-06drm/i915: split out i915_gem.c declarations to i915_gem.hJani Nikula2-36/+43
2022-09-06drm/i915: un-inline i915_gem_drain_freed_objects()Jani Nikula2-16/+16
2022-09-06drm/i915: un-inline i915_gem_drain_workqueue()Jani Nikula2-21/+23
2022-09-06drm/i915: remove unused i915_gem_set_global_seqno() declarationJani Nikula1-2/+0
2022-09-06drm/i915: remove unused macro I915_GTT_OFFSET_NONEJani Nikula1-2/+0
2022-09-06drm/i915: Add DSC support to MST pathStanislav Lisovskiy3-42/+174
2022-09-06drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate functionStanislav Lisovskiy1-13/+41
2022-09-06drm/i915: Fix intel_dp_mst_compute_link_configStanislav Lisovskiy1-2/+14
2022-09-05drm/i915/fbdev: do not create fbdev if HPD is suspendedAndrzej Hajda1-0/+6
2022-09-05drm/i915/fbdev: suspend HPD before fbdev unregistrationAndrzej Hajda1-2/+4
2022-09-05drm/i915/hpd: suspend MST at the end of intel_modeset_driver_removeAndrzej Hajda1-7/+7
2022-09-05drm/i915: Parse DP/eDP max lane count from VBTVille Syrjälä3-1/+29
2022-09-05drm/i915: Rename some VBT bitsVille Syrjälä1-2/+2
2022-09-05drm/i915: Define all possible VBT device handlesVille Syrjälä1-0/+9
2022-09-05drm/i915: Define more VBT driver features block bitsVille Syrjälä1-4/+10
2022-09-05drm/i915: Document the sets of bits in the driver features blockVille Syrjälä1-0/+7
2022-09-05drm/i915: Define VBT max HDMI FRL rate bitsVille Syrjälä1-2/+4
2022-09-05drm/i915: Add the VBT LTTPR transparent vs. non-transparent bitsVille Syrjälä1-1/+2
2022-09-05drm/i915: Define VBT eDP/DP max lane count bitsVille Syrjälä1-1/+1
2022-09-05drm/i915: Properly define the DP redriver VBT bitsVille Syrjälä1-5/+11
2022-09-05drm/i915: Add some more VBT version number commentsVille Syrjälä1-38/+38
2022-09-05drm/i915: Unify VBT version number commentsVille Syrjälä1-96/+110
2022-09-05drm/i915: Start using REG_BIT* macros with CDCLK registersStanislav Lisovskiy1-10/+10
2022-09-03Revert "drm/i915/display: Re-add check for low voltage sku for max dp source rate"Ville Syrjälä1-29/+3
2022-09-03drm/i915: Implement WaEdpLinkRateDataReloadVille Syrjälä1-0/+22
2022-09-02drm/i915/bios: Use hardcoded fp_timing size for generating LFP data pointersVille Syrjälä1-28/+18
2022-09-02drm/i915/bios: Validate fp_timing terminator presenceVille Syrjälä1-28/+32
2022-09-01drm/i915/display: Fix warning callstack for imbalance wakerefMitul Golani1-4/+8
2022-08-31drm/i915: Allow more varied alternate fixed modes for panelsVille Syrjälä1-19/+6
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