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2022-02-09drm/i915: group i915_drv.h forward declarations togetherJani Nikula1-25/+19
2022-02-09gpio: sim: fix hogs with custom chip labelsBartosz Golaszewski1-4/+15
2022-02-09gpiolib: make struct comments into real kernel docsBartosz Golaszewski1-0/+34
2022-02-09mtd: nand: ecc: Provide a helper to retrieve a pilelined engine deviceMiquel Raynal1-0/+31
2022-02-09mtd: nand: mxic-ecc: Add Macronix external ECC engine supportMiquel Raynal3-0/+702
2022-02-09mtd: rawnand: protect access to rawnand devices while in suspendSean Nyekjaer1-24/+20
2022-02-09cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklistStefan Agner1-0/+1
2022-02-09cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuseLuca Weiss1-1/+1
2022-02-09cpufreq: replace cpumask_weight with cpumask_empty where appropriateYury Norov2-2/+2
2022-02-09cpufreq: qcom-hw: Delay enabling throttle_irqBjorn Andersson1-1/+10
2022-02-09cpufreq: Reintroduce ready() callbackBjorn Andersson1-0/+4
2022-02-08drm/i915/guc: Use a single pass to calculate regsetLucas De Marchi2-45/+90
2022-02-08drm/i915/guc: Prepare for error propagationLucas De Marchi1-13/+18
2022-02-08cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron1-2/+2
2022-02-08cxl/core/port: Handle invalid decodersDan Williams1-6/+30
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams2-2/+5
2022-02-09hwmon: peci: Add dimmtemp driverIwona Winiarska3-0/+645
2022-02-09hwmon: peci: Add cputemp driverIwona Winiarska6-0/+676
2022-02-09peci: Add peci-cpu driverIwona Winiarska6-0/+601
2022-02-09peci: Add support for PECI device driversIwona Winiarska4-0/+462
2022-02-09peci: Add sysfs interface for PECI busIwona Winiarska5-2/+91
2022-02-09peci: Add device detectionIwona Winiarska5-1/+223
2022-02-09peci: Add peci-aspeed controller driverJae Hyun Yoo5-0/+629
2022-02-09peci: Add core infrastructureIwona Winiarska6-0/+198
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky4-16/+73
2022-02-08cxl/core: Move target_list out of base decoder attributesDan Williams1-1/+2
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky9-5/+391
2022-02-08cxl/core/port: Add switch port enumerationDan Williams3-25/+438
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+17
2022-02-08cxl/pci: Emit device serial numberDan Williams3-0/+14
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky2-1/+50
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky3-0/+146
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky2-0/+8
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky2-0/+14
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams7-24/+24
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky8-29/+108
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams1-9/+17
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams8-49/+348
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams6-110/+167
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams4-3/+4
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2-2/+3
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams3-4/+60
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams3-5/+49
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams2-7/+25
2022-02-08cxl: Prove CXL lockingDan Williams6-25/+131
2022-02-08cxl/core: Track port depthBen Widawsky2-0/+4
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky2-6/+8
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams1-1/+1
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky3-11/+92
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky3-18/+35
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