Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2007-07-24 | Blackfin arch: setup aliases for some core Core A MMRs | 2 | -0/+10 | |
2007-07-12 | Blackfin arch: clean up some coding style issues | 1 | -1/+0 | |
2007-07-12 | Blackfin arch: Add Support for Peripheral PortMux and resouce allocation | 1 | -0/+87 | |
2007-06-21 | Blackfin arch: add missing implementations SIC_IWR crosses several registers | 1 | -3/+7 | |
2007-07-12 | Blackfin arch: initial supporting for BF548-EZKIT | 1 | -0/+3 | |
2007-06-21 | Blackfin arch: add missing braces around array bfin serial init | 1 | -0/+2 | |
2007-05-21 | Blackfin arch: update blackfin header files to latest one in VDSP. | 1 | -55/+50 | |
2007-05-21 | Blackfin arch: Move write to VR_CTL closer to IDLE | 1 | -2/+4 | |
2007-05-07 | blackfin architecture | 10 | -0/+4894 |