aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx53-m53evk.dts
blob: d5d146a8b149cd14601cef1b26857002d27eec9b (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
/*
 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx53.dtsi"

/ {
	model = "DENX M53EVK";
	compatible = "denx,imx53-m53evk", "fsl,imx53";

	memory {
		reg = <0x70000000 0x20000000>,
		      <0xb0000000 0x20000000>;
	};

	soc {
		display1: display@di1 {
			compatible = "fsl,imx-parallel-display";
			interface-pix-fmt = "bgr666";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ipu_disp1>;

			display-timings {
				800x480p60 {
					native-mode;
					clock-frequency = <31500000>;
					hactive = <800>;
					vactive = <480>;
					hfront-porch = <40>;
					hback-porch = <88>;
					hsync-len = <128>;
					vback-porch = <33>;
					vfront-porch = <9>;
					vsync-len = <3>;
					vsync-active = <1>;
				};
			};
		};

		port {
			display1_in: endpoint {
				remote-endpoint = <&ipu_di1_disp1>;
			};
		};
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 3000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		power-supply = <&reg_backlight>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pin_gpio>;

		user1 {
			label = "user1";
			gpios = <&gpio2 8 0>;
			linux,default-trigger = "heartbeat";
		};

		user2 {
			label = "user2";
			gpios = <&gpio2 9 0>;
			linux,default-trigger = "heartbeat";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3p2v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3P2V";
			regulator-min-microvolt = <3200000>;
			regulator-max-microvolt = <3200000>;
			regulator-always-on;
		};


		reg_backlight: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "lcd-supply";
			regulator-min-microvolt = <3200000>;
			regulator-max-microvolt = <3200000>;
			regulator-always-on;
		};

		reg_usbh1_vbus: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 2 0>;
		};
	};

	sound {
		compatible = "fsl,imx53-m53evk-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx53-m53evk-sgtl5000";
		ssi-controller = <&ssi2>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Ext Spk", "LINE_OUT";
		mux-int-port = <2>;
		mux-ext-port = <4>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can2>;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio1 1 0>;
	wp-gpios = <&gpio1 9 0>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rmii";
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	sgtl5000: codec@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		VDDA-supply = <&reg_3p2v>;
		VDDIO-supply = <&reg_3p2v>;
		clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "okay";

	stmpe610@41 {
		compatible = "st,stmpe610";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x41>;
		id = <0>;
		blocks = <0x5>;
		interrupts = <6 0x0>;
		interrupt-parent = <&gpio7>;
		irq-trigger = <0x1>;

		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			reg = <0>;
			st,sample-time = <4>;
			st,mod-12b = <1>;
			st,ref-sel = <0>;
			st,adc-freq = <1>;
			st,ave-ctrl = <3>;
			st,touch-det-delay = <3>;
			st,settling = <4>;
			st,fraction-z = <7>;
			st,i-drive = <1>;
		};
	};

	eeprom: eeprom@50 {
		compatible = "atmel,24c128";
		reg = <0x50>;
		pagesize = <32>;
	};

	rtc: rtc@68 {
		compatible = "stm,m41t62";
		reg = <0x68>;
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx53-m53evk {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK	0x80000000
				MX53_PAD_EIM_EB3__GPIO2_31		0x80000000
				MX53_PAD_PATA_DA_0__GPIO7_6		0x80000000
				MX53_PAD_GPIO_2__GPIO1_2		0x80000000
				MX53_PAD_GPIO_3__USBOH3_USBH1_OC	0x80000000
			>;
		};

		led_pin_gpio: led_gpio@0 {
			fsl,pins = <
				MX53_PAD_PATA_DATA8__GPIO2_8		0x80000000
				MX53_PAD_PATA_DATA9__GPIO2_9		0x80000000
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC	0x80000000
				MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD	0x80000000
				MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS	0x80000000
				MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD	0x80000000
			>;
		};

		pinctrl_can1: can1grp {
			fsl,pins = <
				MX53_PAD_GPIO_7__CAN1_TXCAN		0x80000000
				MX53_PAD_GPIO_8__CAN1_RXCAN		0x80000000
			>;
		};

		pinctrl_can2: can2grp {
			fsl,pins = <
				MX53_PAD_KEY_COL4__CAN2_TXCAN		0x80000000
				MX53_PAD_KEY_ROW4__CAN2_RXCAN		0x80000000
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000
				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000
				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000
				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000
				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000
				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000
				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000
				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000
				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX53_PAD_EIM_D21__I2C1_SCL		0xc0000000
				MX53_PAD_EIM_D28__I2C1_SDA		0xc0000000
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX53_PAD_EIM_D16__I2C2_SDA		0xc0000000
				MX53_PAD_EIM_EB2__I2C2_SCL		0xc0000000
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX53_PAD_GPIO_6__I2C3_SDA		0xc0000000
				MX53_PAD_GPIO_5__I2C3_SCL		0xc0000000
			>;
		};

		pinctrl_ipu_disp1: ipudisp1grp {
			fsl,pins = <
				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0	0x5
				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1	0x5
				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2	0x5
				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3	0x5
				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4	0x5
				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5	0x5
				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6	0x5
				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7	0x5
				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8	0x5
				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9	0x5
				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10	0x5
				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11	0x5
				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12	0x5
				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13	0x5
				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14	0x5
				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15	0x5
				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16	0x5
				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17	0x5
				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18	0x5
				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19	0x5
				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20	0x5
				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21	0x5
				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22	0x5
				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23	0x5
				MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK	0x5
				MX53_PAD_EIM_DA13__IPU_DI1_D0_CS	0x5
				MX53_PAD_EIM_DA14__IPU_DI1_D1_CS	0x5
				MX53_PAD_EIM_DA15__IPU_DI1_PIN1		0x5
				MX53_PAD_EIM_DA11__IPU_DI1_PIN2		0x5
				MX53_PAD_EIM_DA12__IPU_DI1_PIN3		0x5
				MX53_PAD_EIM_A25__IPU_DI1_PIN12		0x5
				MX53_PAD_EIM_DA10__IPU_DI1_PIN15	0x5
			>;
		};

		pinctrl_nand: nandgrp {
			fsl,pins = <
				MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B	0x4
				MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B	0x4
				MX53_PAD_NANDF_CLE__EMI_NANDF_CLE	0x4
				MX53_PAD_NANDF_ALE__EMI_NANDF_ALE	0x4
				MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B	0xe0
				MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0	0xe0
				MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0	0x4
				MX53_PAD_PATA_DATA0__EMI_NANDF_D_0	0xa4
				MX53_PAD_PATA_DATA1__EMI_NANDF_D_1	0xa4
				MX53_PAD_PATA_DATA2__EMI_NANDF_D_2	0xa4
				MX53_PAD_PATA_DATA3__EMI_NANDF_D_3	0xa4
				MX53_PAD_PATA_DATA4__EMI_NANDF_D_4	0xa4
				MX53_PAD_PATA_DATA5__EMI_NANDF_D_5	0xa4
				MX53_PAD_PATA_DATA6__EMI_NANDF_D_6	0xa4
				MX53_PAD_PATA_DATA7__EMI_NANDF_D_7	0xa4
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				MX53_PAD_DISP0_DAT8__PWM1_PWMO		0x5
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX53_PAD_PATA_DIOW__UART1_TXD_MUX	0x1e4
				MX53_PAD_PATA_DMACK__UART1_RXD_MUX	0x1e4
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX	0x1e4
				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX	0x1e4
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX53_PAD_PATA_CS_0__UART3_TXD_MUX	0x1e4
				MX53_PAD_PATA_CS_1__UART3_RXD_MUX	0x1e4
				MX53_PAD_PATA_DA_1__UART3_CTS		0x1e4
				MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
			>;
		};
	};
};

&ipu_di1_disp1 {
	remote-endpoint = <&display1_in>;
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nand>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&sata {
	status = "okay";
};

&ssi2 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usbh1_vbus>;
	phy_type = "utmi";
	status = "okay";
};

&usbotg {
	dr_mode = "peripheral";
	status = "okay";
};