aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/cm-regbits-44xx.h
blob: 4c6c2f7de65bc6a66062079e1dd702f18ea06599 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
/*
 * OMAP44xx Clock Management register bits
 *
 * Copyright (C) 2009-2012 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H

/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_ABE_DYNDEP_SHIFT				3
#define OMAP4430_ABE_DYNDEP_WIDTH				0x1
#define OMAP4430_ABE_DYNDEP_MASK				(1 << 3)

/*
 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_ABE_STATDEP_SHIFT				3
#define OMAP4430_ABE_STATDEP_WIDTH				0x1
#define OMAP4430_ABE_STATDEP_MASK				(1 << 3)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ALWONCORE_DYNDEP_SHIFT				16
#define OMAP4430_ALWONCORE_DYNDEP_WIDTH				0x1
#define OMAP4430_ALWONCORE_DYNDEP_MASK				(1 << 16)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_ALWONCORE_STATDEP_SHIFT			16
#define OMAP4430_ALWONCORE_STATDEP_WIDTH			0x1
#define OMAP4430_ALWONCORE_STATDEP_MASK				(1 << 16)

/*
 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
 */
#define OMAP4430_AUTO_DPLL_MODE_SHIFT				0
#define OMAP4430_AUTO_DPLL_MODE_WIDTH				0x3
#define OMAP4430_AUTO_DPLL_MODE_MASK				(0x7 << 0)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_CEFUSE_DYNDEP_SHIFT				17
#define OMAP4430_CEFUSE_DYNDEP_WIDTH				0x1
#define OMAP4430_CEFUSE_DYNDEP_MASK				(1 << 17)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_CEFUSE_STATDEP_SHIFT				17
#define OMAP4430_CEFUSE_STATDEP_WIDTH				0x1
#define OMAP4430_CEFUSE_STATDEP_MASK				(1 << 17)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT		13
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK			(1 << 13)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT		12
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK		(1 << 12)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK			(1 << 9)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT			11
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK			(1 << 11)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK			(1 << 8)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT		11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK			(1 << 11)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT		12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK		(1 << 12)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT		13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK		(1 << 13)

/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK		(1 << 9)

/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT		12
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK		(1 << 12)

/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK		(1 << 9)

/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT		9
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH		0x1
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK			(1 << 9)

/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK		(1 << 9)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK			(1 << 9)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK			(1 << 9)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT			10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK			(1 << 10)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT			11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK			(1 << 11)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT			12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK			(1 << 12)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT			13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK			(1 << 13)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT			14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK			(1 << 14)

/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT		10
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK		(1 << 10)

/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK			(1 << 9)

/* Used by CM_DUCATI_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK			(1 << 8)

/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK			(1 << 8)

/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT			10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK			(1 << 10)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT		15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK		(1 << 15)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT		10
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK		(1 << 10)

/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT		11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK		(1 << 11)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT		20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK		(1 << 20)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT		26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK			(1 << 26)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT		21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK		(1 << 21)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT		27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK			(1 << 27)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT		13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK		(1 << 13)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT		12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK		(1 << 12)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT		28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK		(1 << 28)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT		29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK		(1 << 29)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT		11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK		(1 << 11)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT		16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK		(1 << 16)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT		17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK		(1 << 17)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT		18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK		(1 << 18)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT		19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK		(1 << 19)

/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK			(1 << 8)

/* Used by CM_IVAHD_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK		(1 << 8)

/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT		10
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK		(1 << 10)

/* Used by CM_L3_1_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK			(1 << 8)

/* Used by CM_L3_2_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK			(1 << 8)

/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK			(1 << 8)

/* Used by CM_SDMA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK			(1 << 8)

/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK			(1 << 8)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK			(1 << 8)

/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK			(1 << 8)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK			(1 << 8)

/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK		(1 << 8)

/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK		(1 << 8)

/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK			(1 << 8)

/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK		(1 << 8)

/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK			(1 << 8)

/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK			(1 << 9)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK			(1 << 9)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK			(1 << 8)

/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK		(1 << 9)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT		12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK			(1 << 12)

/* Used by CM_MPU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK			(1 << 8)

/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK			(1 << 9)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT		16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK		(1 << 16)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT		17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK			(1 << 17)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT		18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK			(1 << 18)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT		19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK			(1 << 19)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT		25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK		(1 << 25)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT		20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK		(1 << 20)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT		21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK		(1 << 21)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT		22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK		(1 << 22)

/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT		24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK			(1 << 24)

/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT			10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK			(1 << 10)

/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT			9
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK			(1 << 9)

/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT		11
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK		(1 << 11)

/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT		10
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK			(1 << 10)

/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT		9
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK			(1 << 9)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT			8
#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK			(1 << 8)

/* Used by CM_TESLA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT		8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK		(1 << 8)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT		22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK			(1 << 22)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT		23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK			(1 << 23)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT		24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK			(1 << 24)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT		10
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK		(1 << 10)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT			14
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK			(1 << 14)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT		15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK		(1 << 15)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT			10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH			0x1
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK			(1 << 10)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT		30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK			(1 << 30)

/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT		25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK		(1 << 25)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT		11
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH		0x1
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK		(1 << 11)

/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT		13
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH		0x1
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK			(1 << 13)

/*
 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
 * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
 */
#define OMAP4430_CLKSEL_SHIFT					24
#define OMAP4430_CLKSEL_WIDTH					0x1
#define OMAP4430_CLKSEL_MASK					(1 << 24)

/*
 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
 */
#define OMAP4430_CLKSEL_0_0_SHIFT				0
#define OMAP4430_CLKSEL_0_0_WIDTH				0x1
#define OMAP4430_CLKSEL_0_0_MASK				(1 << 0)

/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
#define OMAP4430_CLKSEL_0_1_SHIFT				0
#define OMAP4430_CLKSEL_0_1_WIDTH				0x2
#define OMAP4430_CLKSEL_0_1_MASK				(0x3 << 0)

/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
#define OMAP4430_CLKSEL_24_25_SHIFT				24
#define OMAP4430_CLKSEL_24_25_WIDTH				0x2
#define OMAP4430_CLKSEL_24_25_MASK				(0x3 << 24)

/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_CLKSEL_60M_SHIFT				24
#define OMAP4430_CLKSEL_60M_WIDTH				0x1
#define OMAP4430_CLKSEL_60M_MASK				(1 << 24)

/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT			25
#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH			0x1
#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK			(1 << 25)

/* Used by CM1_ABE_AESS_CLKCTRL */
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24
#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH				0x1
#define OMAP4430_CLKSEL_AESS_FCLK_MASK				(1 << 24)

/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_CORE_SHIFT				0
#define OMAP4430_CLKSEL_CORE_WIDTH				0x1
#define OMAP4430_CLKSEL_CORE_MASK				(1 << 0)

/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_CORE_1_1_SHIFT				1
#define OMAP4430_CLKSEL_CORE_1_1_WIDTH				0x1
#define OMAP4430_CLKSEL_CORE_1_1_MASK				(1 << 1)

/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_CLKSEL_DIV_SHIFT				24
#define OMAP4430_CLKSEL_DIV_WIDTH				0x1
#define OMAP4430_CLKSEL_DIV_MASK				(1 << 24)

/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT			24
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH			0x1
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK			(1 << 24)

/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP4430_CLKSEL_FCLK_SHIFT				24
#define OMAP4430_CLKSEL_FCLK_WIDTH				0x2
#define OMAP4430_CLKSEL_FCLK_MASK				(0x3 << 24)

/* Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT			25
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH			0x1
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK			(1 << 25)

/*
 * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 * CM1_ABE_MCBSP3_CLKCTRL
 */
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT	26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH	0x2
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK	(0x3 << 26)

/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L3_SHIFT				4
#define OMAP4430_CLKSEL_L3_WIDTH				0x1
#define OMAP4430_CLKSEL_L3_MASK					(1 << 4)

/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT				2
#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH				0x1
#define OMAP4430_CLKSEL_L3_SHADOW_MASK				(1 << 2)

/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L4_SHIFT				8
#define OMAP4430_CLKSEL_L4_WIDTH				0x1
#define OMAP4430_CLKSEL_L4_MASK					(1 << 8)

/* Used by CM_CLKSEL_ABE */
#define OMAP4430_CLKSEL_OPP_SHIFT				0
#define OMAP4430_CLKSEL_OPP_WIDTH				0x2
#define OMAP4430_CLKSEL_OPP_MASK				(0x3 << 0)

/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT			27
#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH			0x3
#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK			(0x7 << 27)

/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT			24
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH			0x3
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK			(0x7 << 24)

/* Used by CM_GFX_GFX_CLKCTRL */
#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT				24
#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH				0x1
#define OMAP4430_CLKSEL_SGX_FCLK_MASK				(1 << 24)

/*
 * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
 */
#define OMAP4430_CLKSEL_SOURCE_SHIFT				24
#define OMAP4430_CLKSEL_SOURCE_WIDTH				0x2
#define OMAP4430_CLKSEL_SOURCE_MASK				(0x3 << 24)

/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT			24
#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH			0x1
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK			(1 << 24)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT				24
#define OMAP4430_CLKSEL_UTMI_P1_WIDTH				0x1
#define OMAP4430_CLKSEL_UTMI_P1_MASK				(1 << 24)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT				25
#define OMAP4430_CLKSEL_UTMI_P2_WIDTH				0x1
#define OMAP4430_CLKSEL_UTMI_P2_MASK				(1 << 25)

/*
 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
 */
#define OMAP4430_CLKTRCTRL_SHIFT				0
#define OMAP4430_CLKTRCTRL_WIDTH				0x2
#define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)

/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT			0
#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH			0x7
#define OMAP4430_CORE_DPLL_EMU_DIV_MASK				(0x7f << 0)

/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT			8
#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH			0xb
#define OMAP4430_CORE_DPLL_EMU_MULT_MASK			(0x7ff << 8)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_CUSTOM_SHIFT					6
#define OMAP4430_CUSTOM_WIDTH					0x2
#define OMAP4430_CUSTOM_MASK					(0x3 << 6)

/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_D2D_DYNDEP_SHIFT				18
#define OMAP4430_D2D_DYNDEP_WIDTH				0x1
#define OMAP4430_D2D_DYNDEP_MASK				(1 << 18)

/* Used by CM_MPU_STATICDEP */
#define OMAP4430_D2D_STATDEP_SHIFT				18
#define OMAP4430_D2D_STATDEP_WIDTH				0x1
#define OMAP4430_D2D_STATDEP_MASK				(1 << 18)

/* Used by CM_CLKSEL_DPLL_MPU */
#define OMAP4460_DCC_COUNT_MAX_SHIFT				24
#define OMAP4460_DCC_COUNT_MAX_WIDTH				0x8
#define OMAP4460_DCC_COUNT_MAX_MASK				(0xff << 24)

/* Used by CM_CLKSEL_DPLL_MPU */
#define OMAP4460_DCC_EN_SHIFT					22
#define OMAP4460_DCC_EN_MASK					(1 << 22)

/*
 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
 */
#define OMAP4430_DELTAMSTEP_SHIFT				0
#define OMAP4430_DELTAMSTEP_WIDTH				0x14
#define OMAP4430_DELTAMSTEP_MASK				(0xfffff << 0)

/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
#define OMAP4460_DELTAMSTEP_0_20_SHIFT				0
#define OMAP4460_DELTAMSTEP_0_20_WIDTH				0x15
#define OMAP4460_DELTAMSTEP_0_20_MASK				(0x1fffff << 0)

/* Used by CM_DLL_CTRL */
#define OMAP4430_DLL_OVERRIDE_SHIFT				0
#define OMAP4430_DLL_OVERRIDE_WIDTH				0x1
#define OMAP4430_DLL_OVERRIDE_MASK				(1 << 0)

/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT				2
#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH				0x1
#define OMAP4430_DLL_OVERRIDE_2_2_MASK				(1 << 2)

/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_RESET_SHIFT				3
#define OMAP4430_DLL_RESET_WIDTH				0x1
#define OMAP4430_DLL_RESET_MASK					(1 << 3)

/*
 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
 */
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23
#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH				0x1
#define OMAP4430_DPLL_BYP_CLKSEL_MASK				(1 << 23)

/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT			8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH			0x1
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK			(1 << 8)

/* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT			20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK			(1 << 20)

/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT			0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH			0x5
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)

/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT			5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK			(1 << 5)

/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK			(1 << 8)

/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT			10
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)

/*
 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0
#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH				0x5
#define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)

/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT			0
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH			0x7
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)

/*
 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT			5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK			(1 << 5)

/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT		7
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH		0x1
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK		(1 << 7)

/*
 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 */
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT			8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH			0x1
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)

/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT			8
#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH			0x3
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK				(0x7 << 8)

/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT				11
#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH				0x5
#define OMAP4430_DPLL_CORE_M2_DIV_MASK				(0x1f << 11)

/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT				3
#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH				0x5
#define OMAP4430_DPLL_CORE_M5_DIV_MASK				(0x1f << 3)

/*
 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 * CM_CLKSEL_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_DIV_SHIFT					0
#define OMAP4430_DPLL_DIV_WIDTH					0x7
#define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)

/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_DIV_0_7_SHIFT				0
#define OMAP4430_DPLL_DIV_0_7_WIDTH				0x8
#define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 */
#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT			8
#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH			0x1
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK			(1 << 8)

/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT			3
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH			0x1
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK			(1 << 3)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
#define OMAP4430_DPLL_EN_SHIFT					0
#define OMAP4430_DPLL_EN_WIDTH					0x3
#define OMAP4430_DPLL_EN_MASK					(0x7 << 0)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_LPMODE_EN_SHIFT				10
#define OMAP4430_DPLL_LPMODE_EN_WIDTH				0x1
#define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)

/*
 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 * CM_CLKSEL_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_MULT_SHIFT				8
#define OMAP4430_DPLL_MULT_WIDTH				0xb
#define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)

/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_MULT_USB_SHIFT				8
#define OMAP4430_DPLL_MULT_USB_WIDTH				0xc
#define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO
 */
#define OMAP4430_DPLL_REGM4XEN_SHIFT				11
#define OMAP4430_DPLL_REGM4XEN_WIDTH				0x1
#define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)

/* Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_SD_DIV_SHIFT				24
#define OMAP4430_DPLL_SD_DIV_WIDTH				0x8
#define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
#define OMAP4430_DPLL_SSC_ACK_SHIFT				13
#define OMAP4430_DPLL_SSC_ACK_WIDTH				0x1
#define OMAP4430_DPLL_SSC_ACK_MASK				(1 << 13)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT			14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH			0x1
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK			(1 << 14)

/*
 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 */
#define OMAP4430_DPLL_SSC_EN_SHIFT				12
#define OMAP4430_DPLL_SSC_EN_WIDTH				0x1
#define OMAP4430_DPLL_SSC_EN_MASK				(1 << 12)

/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_DSS_DYNDEP_SHIFT				8
#define OMAP4430_DSS_DYNDEP_WIDTH				0x1
#define OMAP4430_DSS_DYNDEP_MASK				(1 << 8)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DSS_STATDEP_SHIFT				8
#define OMAP4430_DSS_STATDEP_WIDTH				0x1
#define OMAP4430_DSS_STATDEP_MASK				(1 << 8)

/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_DUCATI_DYNDEP_SHIFT				0
#define OMAP4430_DUCATI_DYNDEP_WIDTH				0x1
#define OMAP4430_DUCATI_DYNDEP_MASK				(1 << 0)

/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DUCATI_STATDEP_SHIFT				0
#define OMAP4430_DUCATI_STATDEP_WIDTH				0x1
#define OMAP4430_DUCATI_STATDEP_MASK				(1 << 0)

/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_FREQ_UPDATE_SHIFT				0
#define OMAP4430_FREQ_UPDATE_WIDTH				0x1
#define OMAP4430_FREQ_UPDATE_MASK				(1 << 0)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_FUNC_SHIFT					16
#define OMAP4430_FUNC_WIDTH					0xc
#define OMAP4430_FUNC_MASK					(0xfff << 16)

/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_GFX_DYNDEP_SHIFT				10
#define OMAP4430_GFX_DYNDEP_WIDTH				0x1
#define OMAP4430_GFX_DYNDEP_MASK				(1 << 10)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_GFX_STATDEP_SHIFT				10
#define OMAP4430_GFX_STATDEP_WIDTH				0x1
#define OMAP4430_GFX_STATDEP_MASK				(1 << 10)

/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT				0
#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH				0x1
#define OMAP4430_GPMC_FREQ_UPDATE_MASK				(1 << 0)

/*
 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 * CM_DIV_M4_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT			0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH			0x5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)

/*
 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 * CM_DIV_M4_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT		5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK		(1 << 5)

/*
 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 * CM_DIV_M4_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT		8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK		(1 << 8)

/*
 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 * CM_DIV_M4_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT			12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH			0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK			(1 << 12)

/*
 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 * CM_DIV_M5_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT			0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH			0x5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK			(0x1f << 0)

/*
 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 * CM_DIV_M5_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT		5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK		(1 << 5)

/*
 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 * CM_DIV_M5_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT		8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK		(1 << 8)

/*
 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 * CM_DIV_M5_DPLL_PER
 */
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT			12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH			0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK			(1 << 12)

/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT			0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH			0x5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK			(0x1f << 0)

/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT		5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK		(1 << 5)

/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT		8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK		(1 << 8)

/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT			12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH			0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK			(1 << 12)

/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT			0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH			0x5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK			(0x1f << 0)

/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT		5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK		(1 << 5)

/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT		8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH		0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK		(1 << 8)

/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT			12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH			0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK			(1 << 12)

/*
 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 */
#define OMAP4430_IDLEST_SHIFT					16
#define OMAP4430_IDLEST_WIDTH					0x2
#define OMAP4430_IDLEST_MASK					(0x3 << 16)

/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ISS_DYNDEP_SHIFT				9
#define OMAP4430_ISS_DYNDEP_WIDTH				0x1
#define OMAP4430_ISS_DYNDEP_MASK				(1 << 9)

/*
 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 * CM_TESLA_STATICDEP
 */
#define OMAP4430_ISS_STATDEP_SHIFT				9
#define OMAP4430_ISS_STATDEP_WIDTH				0x1
#define OMAP4430_ISS_STATDEP_MASK				(1 << 9)

/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_IVAHD_DYNDEP_SHIFT				2
#define OMAP4430_IVAHD_DYNDEP_WIDTH				0x1
#define OMAP4430_IVAHD_DYNDEP_MASK				(1 << 2)

/*
 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_IVAHD_STATDEP_SHIFT				2
#define OMAP4430_IVAHD_STATDEP_WIDTH				0x1
#define OMAP4430_IVAHD_STATDEP_MASK				(1 << 2)

/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L3INIT_DYNDEP_SHIFT				7
#define OMAP4430_L3INIT_DYNDEP_WIDTH				0x1
#define OMAP4430_L3INIT_DYNDEP_MASK				(1 << 7)

/*
 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L3INIT_STATDEP_SHIFT				7
#define OMAP4430_L3INIT_STATDEP_WIDTH				0x1
#define OMAP4430_L3INIT_STATDEP_MASK				(1 << 7)

/*
 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 */
#define OMAP4430_L3_1_DYNDEP_SHIFT				5
#define OMAP4430_L3_1_DYNDEP_WIDTH				0x1
#define OMAP4430_L3_1_DYNDEP_MASK				(1 << 5)

/*
 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L3_1_STATDEP_SHIFT				5
#define OMAP4430_L3_1_STATDEP_WIDTH				0x1
#define OMAP4430_L3_1_STATDEP_MASK				(1 << 5)

/*
 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
 */
#define OMAP4430_L3_2_DYNDEP_SHIFT				6
#define OMAP4430_L3_2_DYNDEP_WIDTH				0x1
#define OMAP4430_L3_2_DYNDEP_MASK				(1 << 6)

/*
 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L3_2_STATDEP_SHIFT				6
#define OMAP4430_L3_2_STATDEP_WIDTH				0x1
#define OMAP4430_L3_2_STATDEP_MASK				(1 << 6)

/* Used by CM_L3_1_DYNAMICDEP */
#define OMAP4430_L4CFG_DYNDEP_SHIFT				12
#define OMAP4430_L4CFG_DYNDEP_WIDTH				0x1
#define OMAP4430_L4CFG_DYNDEP_MASK				(1 << 12)

/*
 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L4CFG_STATDEP_SHIFT				12
#define OMAP4430_L4CFG_STATDEP_WIDTH				0x1
#define OMAP4430_L4CFG_STATDEP_MASK				(1 << 12)

/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_L4PER_DYNDEP_SHIFT				13
#define OMAP4430_L4PER_DYNDEP_WIDTH				0x1
#define OMAP4430_L4PER_DYNDEP_MASK				(1 << 13)

/*
 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L4PER_STATDEP_SHIFT				13
#define OMAP4430_L4PER_STATDEP_WIDTH				0x1
#define OMAP4430_L4PER_STATDEP_MASK				(1 << 13)

/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L4SEC_DYNDEP_SHIFT				14
#define OMAP4430_L4SEC_DYNDEP_WIDTH				0x1
#define OMAP4430_L4SEC_DYNDEP_MASK				(1 << 14)

/*
 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP
 */
#define OMAP4430_L4SEC_STATDEP_SHIFT				14
#define OMAP4430_L4SEC_STATDEP_WIDTH				0x1
#define OMAP4430_L4SEC_STATDEP_MASK				(1 << 14)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_L4WKUP_DYNDEP_SHIFT				15
#define OMAP4430_L4WKUP_DYNDEP_WIDTH				0x1
#define OMAP4430_L4WKUP_DYNDEP_MASK				(1 << 15)

/*
 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_L4WKUP_STATDEP_SHIFT				15
#define OMAP4430_L4WKUP_STATDEP_WIDTH				0x1
#define OMAP4430_L4WKUP_STATDEP_MASK				(1 << 15)

/*
 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 * CM_MPU_DYNAMICDEP
 */
#define OMAP4430_MEMIF_DYNDEP_SHIFT				4
#define OMAP4430_MEMIF_DYNDEP_WIDTH				0x1
#define OMAP4430_MEMIF_DYNDEP_MASK				(1 << 4)

/*
 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 */
#define OMAP4430_MEMIF_STATDEP_SHIFT				4
#define OMAP4430_MEMIF_STATDEP_WIDTH				0x1
#define OMAP4430_MEMIF_STATDEP_MASK				(1 << 4)

/*
 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
 */
#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT			8
#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH			0x3
#define OMAP4430_MODFREQDIV_EXPONENT_MASK			(0x7 << 8)

/*
 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
 */
#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT			0
#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH			0x7
#define OMAP4430_MODFREQDIV_MANTISSA_MASK			(0x7f << 0)

/*
 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 */
#define OMAP4430_MODULEMODE_SHIFT				0
#define OMAP4430_MODULEMODE_WIDTH				0x2
#define OMAP4430_MODULEMODE_MASK				(0x3 << 0)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4460_MPU_DYNDEP_SHIFT				19
#define OMAP4460_MPU_DYNDEP_WIDTH				0x1
#define OMAP4460_MPU_DYNDEP_MASK				(1 << 19)

/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK			(1 << 9)

/* Used by CM_WKUP_BANDGAP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT			8
#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK			(1 << 8)

/* Used by CM_ALWON_USBPHY_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT				8
#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_CLK32K_MASK				(1 << 8)

/* Used by CM_CAM_ISS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK				(1 << 8)

/*
 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
 * CM_WKUP_GPIO1_CLKCTRL
 */
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT				8
#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_DBCLK_MASK				(1 << 8)

/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK				(1 << 8)

/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT				8
#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_DSSCLK_MASK				(1 << 8)

/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK_SHIFT				8
#define OMAP4430_OPTFCLKEN_FCLK_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_FCLK_MASK				(1 << 8)

/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT				8
#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_FCLK0_MASK				(1 << 8)

/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT				9
#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_FCLK1_MASK				(1 << 9)

/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT				10
#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_FCLK2_MASK				(1 << 10)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT			15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK			(1 << 15)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT		13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH		0x1
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK			(1 << 13)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT		14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH		0x1
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK			(1 << 14)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT			11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK			(1 << 11)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT			12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK			(1 << 12)

/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK			(1 << 8)

/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT		9
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH		0x1
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK			(1 << 9)

/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT			8
#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_PHY_48M_MASK				(1 << 8)

/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT			10
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK			(1 << 10)

/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT		11
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH		0x1
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK		(1 << 11)

/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10
#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK				(1 << 10)

/* Used by CM_WKUP_BANDGAP_CLKCTRL */
#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8
#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH			0x1
#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK				(1 << 8)

/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11
#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK				(1 << 11)

/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK			(1 << 8)

/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK			(1 << 8)

/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT			9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK			(1 << 9)

/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT			10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK			(1 << 10)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT			8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK			(1 << 8)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT			9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK			(1 << 9)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT			10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH			0x1
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK			(1 << 10)

/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_OPTFCLKEN_XCLK_SHIFT				8
#define OMAP4430_OPTFCLKEN_XCLK_WIDTH				0x1
#define OMAP4430_OPTFCLKEN_XCLK_MASK				(1 << 8)

/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_OVERRIDE_ENABLE_SHIFT				19
#define OMAP4430_OVERRIDE_ENABLE_WIDTH				0x1
#define OMAP4430_OVERRIDE_ENABLE_MASK				(1 << 19)

/* Used by CM_CLKSEL_ABE */
#define OMAP4430_PAD_CLKS_GATE_SHIFT				8
#define OMAP4430_PAD_CLKS_GATE_WIDTH				0x1
#define OMAP4430_PAD_CLKS_GATE_MASK				(1 << 8)

/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
#define OMAP4430_PERF_CURRENT_SHIFT				0
#define OMAP4430_PERF_CURRENT_WIDTH				0x8
#define OMAP4430_PERF_CURRENT_MASK				(0xff << 0)

/*
 * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
 * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
 * CM_IVA_DVFS_PERF_TESLA
 */
#define OMAP4430_PERF_REQ_SHIFT					0
#define OMAP4430_PERF_REQ_WIDTH					0x8
#define OMAP4430_PERF_REQ_MASK					(0xff << 0)

/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE1_COMPLETED_SHIFT				0
#define OMAP4430_PHASE1_COMPLETED_WIDTH				0x1
#define OMAP4430_PHASE1_COMPLETED_MASK				(1 << 0)

/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2A_COMPLETED_SHIFT			1
#define OMAP4430_PHASE2A_COMPLETED_WIDTH			0x1
#define OMAP4430_PHASE2A_COMPLETED_MASK				(1 << 1)

/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2B_COMPLETED_SHIFT			2
#define OMAP4430_PHASE2B_COMPLETED_WIDTH			0x1
#define OMAP4430_PHASE2B_COMPLETED_MASK				(1 << 2)

/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT				20
#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH				0x2
#define OMAP4430_PMD_STM_MUX_CTRL_MASK				(0x3 << 20)

/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT			22
#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH			0x2
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK			(0x3 << 22)

/* Used by CM_DYN_DEP_PRESCAL */
#define OMAP4430_PRESCAL_SHIFT					0
#define OMAP4430_PRESCAL_WIDTH					0x6
#define OMAP4430_PRESCAL_MASK					(0x3f << 0)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_R_RTL_SHIFT					11
#define OMAP4430_R_RTL_WIDTH					0x5
#define OMAP4430_R_RTL_MASK					(0x1f << 11)

/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_SAR_MODE_SHIFT					4
#define OMAP4430_SAR_MODE_WIDTH					0x1
#define OMAP4430_SAR_MODE_MASK					(1 << 4)

/* Used by CM_SCALE_FCLK */
#define OMAP4430_SCALE_FCLK_SHIFT				0
#define OMAP4430_SCALE_FCLK_WIDTH				0x1
#define OMAP4430_SCALE_FCLK_MASK				(1 << 0)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_SCHEME_SHIFT					30
#define OMAP4430_SCHEME_WIDTH					0x2
#define OMAP4430_SCHEME_MASK					(0x3 << 30)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_SDMA_DYNDEP_SHIFT				11
#define OMAP4430_SDMA_DYNDEP_WIDTH				0x1
#define OMAP4430_SDMA_DYNDEP_MASK				(1 << 11)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_SDMA_STATDEP_SHIFT				11
#define OMAP4430_SDMA_STATDEP_WIDTH				0x1
#define OMAP4430_SDMA_STATDEP_MASK				(1 << 11)

/* Used by CM_CLKSEL_ABE */
#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT				10
#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH				0x1
#define OMAP4430_SLIMBUS_CLK_GATE_MASK				(1 << 10)

/*
 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
 */
#define OMAP4430_STBYST_SHIFT					18
#define OMAP4430_STBYST_WIDTH					0x1
#define OMAP4430_STBYST_MASK					(1 << 18)

/*
 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
 */
#define OMAP4430_ST_DPLL_CLK_SHIFT				0
#define OMAP4430_ST_DPLL_CLK_WIDTH				0x1
#define OMAP4430_ST_DPLL_CLK_MASK				(1 << 0)

/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT			9
#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH			0x1
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK				(1 << 9)

/*
 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 */
#define OMAP4430_ST_DPLL_CLKOUT_SHIFT				9
#define OMAP4430_ST_DPLL_CLKOUT_WIDTH				0x1
#define OMAP4430_ST_DPLL_CLKOUT_MASK				(1 << 9)

/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT			9
#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH			0x1
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK				(1 << 9)

/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT				11
#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH				0x1
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK				(1 << 11)

/*
 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 * CM_DIV_M4_DPLL_PER
 */
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT			9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH			0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK			(1 << 9)

/*
 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 * CM_DIV_M5_DPLL_PER
 */
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT			9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH			0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK			(1 << 9)

/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT			9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH			0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK			(1 << 9)

/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT			9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH			0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK			(1 << 9)

/*
 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
 */
#define OMAP4430_ST_MN_BYPASS_SHIFT				8
#define OMAP4430_ST_MN_BYPASS_WIDTH				0x1
#define OMAP4430_ST_MN_BYPASS_MASK				(1 << 8)

/* Used by CM_SYS_CLKSEL */
#define OMAP4430_SYS_CLKSEL_SHIFT				0
#define OMAP4430_SYS_CLKSEL_WIDTH				0x3
#define OMAP4430_SYS_CLKSEL_MASK				(0x7 << 0)

/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_TESLA_DYNDEP_SHIFT				1
#define OMAP4430_TESLA_DYNDEP_WIDTH				0x1
#define OMAP4430_TESLA_DYNDEP_MASK				(1 << 1)

/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_TESLA_STATDEP_SHIFT				1
#define OMAP4430_TESLA_STATDEP_WIDTH				0x1
#define OMAP4430_TESLA_STATDEP_MASK				(1 << 1)

/*
 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 */
#define OMAP4430_WINDOWSIZE_SHIFT				24
#define OMAP4430_WINDOWSIZE_WIDTH				0x4
#define OMAP4430_WINDOWSIZE_MASK				(0xf << 24)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_X_MAJOR_SHIFT					8
#define OMAP4430_X_MAJOR_WIDTH					0x3
#define OMAP4430_X_MAJOR_MASK					(0x7 << 8)

/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_Y_MINOR_SHIFT					0
#define OMAP4430_Y_MINOR_WIDTH					0x6
#define OMAP4430_Y_MINOR_MASK					(0x3f << 0)
#endif