aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/include/asm/uv/uv_mmrs.h
blob: bd5f80e58a236b08961d898f37004670a52e9e02 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV MMR definitions
 *
 * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_X86_UV_UV_MMRS_H
#define _ASM_X86_UV_UV_MMRS_H

/*
 * This file contains MMR definitions for all UV hubs types.
 *
 * To minimize coding differences between hub types, the symbols are
 * grouped by architecture types.
 *
 * UVH  - definitions common to all UV hub types.
 * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3).
 * UV1H - definitions specific to UV type 1 hub.
 * UV2H - definitions specific to UV type 2 hub.
 * UV3H - definitions specific to UV type 3 hub.
 *
 * So in general, MMR addresses and structures are identical on all hubs types.
 * These MMRs are identified as:
 *	#define UVH_xxx		<address>
 *	union uvh_xxx {
 *		unsigned long       v;
 *		struct uvh_int_cmpd_s {
 *		} s;
 *	};
 *
 * If the MMR exists on all hub types but have different addresses:
 *	#define UV1Hxxx	a
 *	#define UV2Hxxx	b
 *	#define UV3Hxxx	c
 *	#define UVHxxx	(is_uv1_hub() ? UV1Hxxx :
 *			(is_uv2_hub() ? UV2Hxxx :
 *					UV3Hxxx))
 *
 * If the MMR exists on all hub types > 1 but have different addresses:
 *	#define UV2Hxxx	b
 *	#define UV3Hxxx	c
 *	#define UVXHxxx (is_uv2_hub() ? UV2Hxxx :
 *					UV3Hxxx))
 *
 *	union uvh_xxx {
 *		unsigned long       v;
 *		struct uvh_xxx_s {	 # Common fields only
 *		} s;
 *		struct uv1h_xxx_s {	 # Full UV1 definition (*)
 *		} s1;
 *		struct uv2h_xxx_s {	 # Full UV2 definition (*)
 *		} s2;
 *		struct uv3h_xxx_s {	 # Full UV3 definition (*)
 *		} s3;
 *	};
 *		(* - if present and different than the common struct)
 *
 * Only essential differences are enumerated. For example, if the address is
 * the same for all UV's, only a single #define is generated. Likewise,
 * if the contents is the same for all hubs, only the "s" structure is
 * generated.
 *
 * If the MMR exists on ONLY 1 type of hub, no generic definition is
 * generated:
 *	#define UVnH_xxx	<uvn address>
 *	union uvnh_xxx {
 *		unsigned long       v;
 *		struct uvh_int_cmpd_s {
 *		} sn;
 *	};
 *
 * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH)
 */

#define UV_MMR_ENABLE		(1UL << 63)

#define UV1_HUB_PART_NUMBER	0x88a5
#define UV2_HUB_PART_NUMBER	0x8eb8
#define UV2_HUB_PART_NUMBER_X	0x1111
#define UV3_HUB_PART_NUMBER	0x9578
#define UV3_HUB_PART_NUMBER_X	0x4321

/* Compat: Indicate which UV Hubs are supported. */
#define UV2_HUB_IS_SUPPORTED	1
#define UV3_HUB_IS_SUPPORTED	1

/* ========================================================================= */
/*                          UVH_BAU_DATA_BROADCAST                           */
/* ========================================================================= */
#define UVH_BAU_DATA_BROADCAST 0x61688UL
#define UVH_BAU_DATA_BROADCAST_32 0x440

#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT		0
#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK		0x0000000000000001UL

union uvh_bau_data_broadcast_u {
	unsigned long	v;
	struct uvh_bau_data_broadcast_s {
		unsigned long	enable:1;			/* RW */
		unsigned long	rsvd_1_63:63;
	} s;
};

/* ========================================================================= */
/*                           UVH_BAU_DATA_CONFIG                             */
/* ========================================================================= */
#define UVH_BAU_DATA_CONFIG 0x61680UL
#define UVH_BAU_DATA_CONFIG_32 0x438

#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT			0
#define UVH_BAU_DATA_CONFIG_DM_SHFT			8
#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT		11
#define UVH_BAU_DATA_CONFIG_STATUS_SHFT			12
#define UVH_BAU_DATA_CONFIG_P_SHFT			13
#define UVH_BAU_DATA_CONFIG_T_SHFT			15
#define UVH_BAU_DATA_CONFIG_M_SHFT			16
#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT		32
#define UVH_BAU_DATA_CONFIG_VECTOR_MASK			0x00000000000000ffUL
#define UVH_BAU_DATA_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_BAU_DATA_CONFIG_STATUS_MASK			0x0000000000001000UL
#define UVH_BAU_DATA_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_BAU_DATA_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_BAU_DATA_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_bau_data_config_u {
	unsigned long	v;
	struct uvh_bau_data_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                           UVH_EVENT_OCCURRED0                             */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0 0x70000UL
#define UVH_EVENT_OCCURRED0_32 0x5e8

#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT		0
#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT		11
#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK		0x0000000000000001UL
#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK		0x0000000000000800UL

#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT		1
#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT		2
#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT		3
#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT		4
#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT		5
#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT		6
#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT		7
#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT		8
#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT		9
#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT		10
#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT		12
#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT		13
#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT		14
#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		15
#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		16
#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT		17
#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT		18
#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT		19
#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT		20
#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT		21
#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	22
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		23
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		24
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		25
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		26
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		27
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		28
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		29
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		30
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		31
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		32
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		33
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		34
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		35
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		36
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		37
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		38
#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		39
#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		40
#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		41
#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		42
#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT		43
#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	44
#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT		45
#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		46
#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		47
#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		48
#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		49
#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT		50
#define UV1H_EVENT_OCCURRED0_RTC0_SHFT			51
#define UV1H_EVENT_OCCURRED0_RTC1_SHFT			52
#define UV1H_EVENT_OCCURRED0_RTC2_SHFT			53
#define UV1H_EVENT_OCCURRED0_RTC3_SHFT			54
#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT		55
#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT	56
#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000002UL
#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000004UL
#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK		0x0000000000000008UL
#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000010UL
#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK		0x0000000000000020UL
#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK		0x0000000000000040UL
#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000080UL
#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000000100UL
#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000000200UL
#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK		0x0000000000000400UL
#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK		0x0000000000001000UL
#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK		0x0000000000002000UL
#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000004000UL
#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000000008000UL
#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000000010000UL
#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK		0x0000000000020000UL
#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000040000UL
#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK		0x0000000000080000UL
#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK		0x0000000000100000UL
#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK		0x0000000000200000UL
#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000000400000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000000800000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000001000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000002000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000004000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000000008000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000000010000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000000020000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000000040000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000000080000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000000100000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000000200000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000000400000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000000800000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000001000000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000002000000000UL
#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000004000000000UL
#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0000008000000000UL
#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0000010000000000UL
#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0000020000000000UL
#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0000040000000000UL
#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK		0x0000080000000000UL
#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0000100000000000UL
#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK		0x0000200000000000UL
#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0000400000000000UL
#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0000800000000000UL
#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0001000000000000UL
#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0002000000000000UL
#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0004000000000000UL
#define UV1H_EVENT_OCCURRED0_RTC0_MASK			0x0008000000000000UL
#define UV1H_EVENT_OCCURRED0_RTC1_MASK			0x0010000000000000UL
#define UV1H_EVENT_OCCURRED0_RTC2_MASK			0x0020000000000000UL
#define UV1H_EVENT_OCCURRED0_RTC3_MASK			0x0040000000000000UL
#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK		0x0080000000000000UL
#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK	0x0100000000000000UL

#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT		1
#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT		2
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT		3
#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT		4
#define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT		5
#define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT		6
#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT		7
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT		8
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT		9
#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT		12
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT		13
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT		14
#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT		15
#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT		16
#define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
#define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
#define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
#define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
#define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
#define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
#define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT		53
#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000004UL
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK		0x0000000000000008UL
#define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK		0x0000000000000010UL
#define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000020UL
#define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000040UL
#define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK		0x0000000000000080UL
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK		0x0000000000000100UL
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000200UL
#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK		0x0000000000001000UL
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK		0x0000000000002000UL
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000004000UL
#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000008000UL
#define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK		0x0000000000010000UL
#define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
#define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
#define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
#define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
#define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
#define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
#define UVXH_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL

union uvh_event_occurred0_u {
	unsigned long	v;
	struct uvh_event_occurred0_s {
		unsigned long	lb_hcerr:1;			/* RW, W1C */
		unsigned long	rsvd_1_10:10;
		unsigned long	rh_aoerr0:1;			/* RW, W1C */
		unsigned long	rsvd_12_63:52;
	} s;
	struct uvxh_event_occurred0_s {
		unsigned long	lb_hcerr:1;			/* RW */
		unsigned long	qp_hcerr:1;			/* RW */
		unsigned long	rh_hcerr:1;			/* RW */
		unsigned long	lh0_hcerr:1;			/* RW */
		unsigned long	lh1_hcerr:1;			/* RW */
		unsigned long	gr0_hcerr:1;			/* RW */
		unsigned long	gr1_hcerr:1;			/* RW */
		unsigned long	ni0_hcerr:1;			/* RW */
		unsigned long	ni1_hcerr:1;			/* RW */
		unsigned long	lb_aoerr0:1;			/* RW */
		unsigned long	qp_aoerr0:1;			/* RW */
		unsigned long	rh_aoerr0:1;			/* RW */
		unsigned long	lh0_aoerr0:1;			/* RW */
		unsigned long	lh1_aoerr0:1;			/* RW */
		unsigned long	gr0_aoerr0:1;			/* RW */
		unsigned long	gr1_aoerr0:1;			/* RW */
		unsigned long	xb_aoerr0:1;			/* RW */
		unsigned long	rt_aoerr0:1;			/* RW */
		unsigned long	ni0_aoerr0:1;			/* RW */
		unsigned long	ni1_aoerr0:1;			/* RW */
		unsigned long	lb_aoerr1:1;			/* RW */
		unsigned long	qp_aoerr1:1;			/* RW */
		unsigned long	rh_aoerr1:1;			/* RW */
		unsigned long	lh0_aoerr1:1;			/* RW */
		unsigned long	lh1_aoerr1:1;			/* RW */
		unsigned long	gr0_aoerr1:1;			/* RW */
		unsigned long	gr1_aoerr1:1;			/* RW */
		unsigned long	xb_aoerr1:1;			/* RW */
		unsigned long	rt_aoerr1:1;			/* RW */
		unsigned long	ni0_aoerr1:1;			/* RW */
		unsigned long	ni1_aoerr1:1;			/* RW */
		unsigned long	system_shutdown_int:1;		/* RW */
		unsigned long	lb_irq_int_0:1;			/* RW */
		unsigned long	lb_irq_int_1:1;			/* RW */
		unsigned long	lb_irq_int_2:1;			/* RW */
		unsigned long	lb_irq_int_3:1;			/* RW */
		unsigned long	lb_irq_int_4:1;			/* RW */
		unsigned long	lb_irq_int_5:1;			/* RW */
		unsigned long	lb_irq_int_6:1;			/* RW */
		unsigned long	lb_irq_int_7:1;			/* RW */
		unsigned long	lb_irq_int_8:1;			/* RW */
		unsigned long	lb_irq_int_9:1;			/* RW */
		unsigned long	lb_irq_int_10:1;		/* RW */
		unsigned long	lb_irq_int_11:1;		/* RW */
		unsigned long	lb_irq_int_12:1;		/* RW */
		unsigned long	lb_irq_int_13:1;		/* RW */
		unsigned long	lb_irq_int_14:1;		/* RW */
		unsigned long	lb_irq_int_15:1;		/* RW */
		unsigned long	l1_nmi_int:1;			/* RW */
		unsigned long	stop_clock:1;			/* RW */
		unsigned long	asic_to_l1:1;			/* RW */
		unsigned long	l1_to_asic:1;			/* RW */
		unsigned long	la_seq_trigger:1;		/* RW */
		unsigned long	ipi_int:1;			/* RW */
		unsigned long	extio_int0:1;			/* RW */
		unsigned long	extio_int1:1;			/* RW */
		unsigned long	extio_int2:1;			/* RW */
		unsigned long	extio_int3:1;			/* RW */
		unsigned long	profile_int:1;			/* RW */
		unsigned long	rsvd_59_63:5;
	} sx;
};

/* ========================================================================= */
/*                        UVH_EVENT_OCCURRED0_ALIAS                          */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0


/* ========================================================================= */
/*                         UVH_GR0_TLB_INT0_CONFIG                           */
/* ========================================================================= */
#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL

#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT		0
#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT			8
#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT		11
#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT		12
#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT			13
#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT			15
#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT			16
#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT		32
#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
#define UVH_GR0_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_GR0_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_GR0_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_gr0_tlb_int0_config_u {
	unsigned long	v;
	struct uvh_gr0_tlb_int0_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                         UVH_GR0_TLB_INT1_CONFIG                           */
/* ========================================================================= */
#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL

#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT		0
#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT			8
#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT		11
#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT		12
#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT			13
#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT			15
#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT			16
#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT		32
#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
#define UVH_GR0_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_GR0_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_GR0_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_gr0_tlb_int1_config_u {
	unsigned long	v;
	struct uvh_gr0_tlb_int1_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                         UVH_GR0_TLB_MMR_CONTROL                           */
/* ========================================================================= */
#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
#define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
#define UVH_GR0_TLB_MMR_CONTROL						\
		(is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :		\
		(is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :		\
				UV3H_GR0_TLB_MMR_CONTROL))

#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL

#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL

#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL

#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL

#define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL

union uvh_gr0_tlb_mmr_control_u {
	unsigned long	v;
	struct uvh_gr0_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	rsvd_32_48:17;
		unsigned long	rsvd_49_51:3;
		unsigned long	rsvd_52_63:12;
	} s;
	struct uv1h_gr0_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	rsvd_32_47:16;
		unsigned long	mmr_inj_con:1;			/* RW */
		unsigned long	rsvd_49_51:3;
		unsigned long	mmr_inj_tlbram:1;		/* RW */
		unsigned long	rsvd_53:1;
		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
		unsigned long	rsvd_55:1;
		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
		unsigned long	rsvd_57_59:3;
		unsigned long	mmr_inj_tlblruv:1;		/* RW */
		unsigned long	rsvd_61_63:3;
	} s1;
	struct uvxh_gr0_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	rsvd_48:1;
		unsigned long	rsvd_49_51:3;
		unsigned long	rsvd_52:1;
		unsigned long	rsvd_53_63:11;
	} sx;
	struct uv2h_gr0_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	mmr_inj_con:1;			/* RW */
		unsigned long	rsvd_49_51:3;
		unsigned long	mmr_inj_tlbram:1;		/* RW */
		unsigned long	rsvd_53_63:11;
	} s2;
	struct uv3h_gr0_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	ecc_sel:1;			/* RW */
		unsigned long	rsvd_22_29:8;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	undef_48:1;			/* Undefined */
		unsigned long	rsvd_49_51:3;
		unsigned long	undef_52:1;			/* Undefined */
		unsigned long	rsvd_53_63:11;
	} s3;
};

/* ========================================================================= */
/*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
/* ========================================================================= */
#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
#define UVH_GR0_TLB_MMR_READ_DATA_HI					\
		(is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :		\
		(is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :		\
				UV3H_GR0_TLB_MMR_READ_DATA_HI))

#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT		43
#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK		0x0000080000000000UL
#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL

union uvh_gr0_tlb_mmr_read_data_hi_u {
	unsigned long	v;
	struct uvh_gr0_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s;
	struct uv1h_gr0_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s1;
	struct uvxh_gr0_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} sx;
	struct uv2h_gr0_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s2;
	struct uv3h_gr0_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	aa_ext:1;			/* RO */
		unsigned long	undef_46_54:9;			/* Undefined */
		unsigned long	way_ecc:9;			/* RO */
	} s3;
};

/* ========================================================================= */
/*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
/* ========================================================================= */
#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
#define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
#define UVH_GR0_TLB_MMR_READ_DATA_LO					\
		(is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :		\
		(is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :		\
				UV3H_GR0_TLB_MMR_READ_DATA_LO))

#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL

#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

union uvh_gr0_tlb_mmr_read_data_lo_u {
	unsigned long	v;
	struct uvh_gr0_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s;
	struct uv1h_gr0_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s1;
	struct uvxh_gr0_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} sx;
	struct uv2h_gr0_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s2;
	struct uv3h_gr0_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s3;
};

/* ========================================================================= */
/*                         UVH_GR1_TLB_INT0_CONFIG                           */
/* ========================================================================= */
#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL

#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT		0
#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT			8
#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT		11
#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT		12
#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT			13
#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT			15
#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT			16
#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT		32
#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
#define UVH_GR1_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_GR1_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_GR1_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_gr1_tlb_int0_config_u {
	unsigned long	v;
	struct uvh_gr1_tlb_int0_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                         UVH_GR1_TLB_INT1_CONFIG                           */
/* ========================================================================= */
#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL

#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT		0
#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT			8
#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT		11
#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT		12
#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT			13
#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT			15
#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT			16
#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT		32
#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
#define UVH_GR1_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_GR1_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_GR1_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_gr1_tlb_int1_config_u {
	unsigned long	v;
	struct uvh_gr1_tlb_int1_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                         UVH_GR1_TLB_MMR_CONTROL                           */
/* ========================================================================= */
#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
#define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
#define UVH_GR1_TLB_MMR_CONTROL						\
		(is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :		\
		(is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :		\
				UV3H_GR1_TLB_MMR_CONTROL))

#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL

#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL

#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL

#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL

#define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
#define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
#define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
#define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
#define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
#define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
#define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
#define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL

union uvh_gr1_tlb_mmr_control_u {
	unsigned long	v;
	struct uvh_gr1_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	rsvd_32_48:17;
		unsigned long	rsvd_49_51:3;
		unsigned long	rsvd_52_63:12;
	} s;
	struct uv1h_gr1_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	rsvd_32_47:16;
		unsigned long	mmr_inj_con:1;			/* RW */
		unsigned long	rsvd_49_51:3;
		unsigned long	mmr_inj_tlbram:1;		/* RW */
		unsigned long	rsvd_53:1;
		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
		unsigned long	rsvd_55:1;
		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
		unsigned long	rsvd_57_59:3;
		unsigned long	mmr_inj_tlblruv:1;		/* RW */
		unsigned long	rsvd_61_63:3;
	} s1;
	struct uvxh_gr1_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	rsvd_48:1;
		unsigned long	rsvd_49_51:3;
		unsigned long	rsvd_52:1;
		unsigned long	rsvd_53_63:11;
	} sx;
	struct uv2h_gr1_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	rsvd_21_29:9;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	mmr_inj_con:1;			/* RW */
		unsigned long	rsvd_49_51:3;
		unsigned long	mmr_inj_tlbram:1;		/* RW */
		unsigned long	rsvd_53_63:11;
	} s2;
	struct uv3h_gr1_tlb_mmr_control_s {
		unsigned long	index:12;			/* RW */
		unsigned long	mem_sel:2;			/* RW */
		unsigned long	rsvd_14_15:2;
		unsigned long	auto_valid_en:1;		/* RW */
		unsigned long	rsvd_17_19:3;
		unsigned long	mmr_hash_index_en:1;		/* RW */
		unsigned long	ecc_sel:1;			/* RW */
		unsigned long	rsvd_22_29:8;
		unsigned long	mmr_write:1;			/* WP */
		unsigned long	mmr_read:1;			/* WP */
		unsigned long	mmr_op_done:1;			/* RW */
		unsigned long	rsvd_33_47:15;
		unsigned long	undef_48:1;			/* Undefined */
		unsigned long	rsvd_49_51:3;
		unsigned long	undef_52:1;			/* Undefined */
		unsigned long	rsvd_53_63:11;
	} s3;
};

/* ========================================================================= */
/*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
/* ========================================================================= */
#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
#define UVH_GR1_TLB_MMR_READ_DATA_HI					\
		(is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :		\
		(is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :		\
				UV3H_GR1_TLB_MMR_READ_DATA_HI))

#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT		43
#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK		0x0000080000000000UL
#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL

#define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL

union uvh_gr1_tlb_mmr_read_data_hi_u {
	unsigned long	v;
	struct uvh_gr1_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s;
	struct uv1h_gr1_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s1;
	struct uvxh_gr1_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} sx;
	struct uv2h_gr1_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	rsvd_45_63:19;
	} s2;
	struct uv3h_gr1_tlb_mmr_read_data_hi_s {
		unsigned long	pfn:41;				/* RO */
		unsigned long	gaa:2;				/* RO */
		unsigned long	dirty:1;			/* RO */
		unsigned long	larger:1;			/* RO */
		unsigned long	aa_ext:1;			/* RO */
		unsigned long	undef_46_54:9;			/* Undefined */
		unsigned long	way_ecc:9;			/* RO */
	} s3;
};

/* ========================================================================= */
/*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
/* ========================================================================= */
#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
#define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
#define UVH_GR1_TLB_MMR_READ_DATA_LO					\
		(is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :		\
		(is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :		\
				UV3H_GR1_TLB_MMR_READ_DATA_LO))

#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL

#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL

union uvh_gr1_tlb_mmr_read_data_lo_u {
	unsigned long	v;
	struct uvh_gr1_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s;
	struct uv1h_gr1_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s1;
	struct uvxh_gr1_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} sx;
	struct uv2h_gr1_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s2;
	struct uv3h_gr1_tlb_mmr_read_data_lo_s {
		unsigned long	vpn:39;				/* RO */
		unsigned long	asid:24;			/* RO */
		unsigned long	valid:1;			/* RO */
	} s3;
};

/* ========================================================================= */
/*                               UVH_INT_CMPB                                */
/* ========================================================================= */
#define UVH_INT_CMPB 0x22080UL

#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT		0
#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK		0x00ffffffffffffffUL

union uvh_int_cmpb_u {
	unsigned long	v;
	struct uvh_int_cmpb_s {
		unsigned long	real_time_cmpb:56;		/* RW */
		unsigned long	rsvd_56_63:8;
	} s;
};

/* ========================================================================= */
/*                               UVH_INT_CMPC                                */
/* ========================================================================= */
#define UVH_INT_CMPC 0x22100UL

#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT		0
#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK		0x00ffffffffffffffUL

#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT		0
#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK		0x00ffffffffffffffUL

union uvh_int_cmpc_u {
	unsigned long	v;
	struct uvh_int_cmpc_s {
		unsigned long	real_time_cmpc:56;		/* RW */
		unsigned long	rsvd_56_63:8;
	} s;
};

/* ========================================================================= */
/*                               UVH_INT_CMPD                                */
/* ========================================================================= */
#define UVH_INT_CMPD 0x22180UL

#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT		0
#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK		0x00ffffffffffffffUL

#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT		0
#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK		0x00ffffffffffffffUL

union uvh_int_cmpd_u {
	unsigned long	v;
	struct uvh_int_cmpd_s {
		unsigned long	real_time_cmpd:56;		/* RW */
		unsigned long	rsvd_56_63:8;
	} s;
};

/* ========================================================================= */
/*                               UVH_IPI_INT                                 */
/* ========================================================================= */
#define UVH_IPI_INT 0x60500UL
#define UVH_IPI_INT_32 0x348

#define UVH_IPI_INT_VECTOR_SHFT				0
#define UVH_IPI_INT_DELIVERY_MODE_SHFT			8
#define UVH_IPI_INT_DESTMODE_SHFT			11
#define UVH_IPI_INT_APIC_ID_SHFT			16
#define UVH_IPI_INT_SEND_SHFT				63
#define UVH_IPI_INT_VECTOR_MASK				0x00000000000000ffUL
#define UVH_IPI_INT_DELIVERY_MODE_MASK			0x0000000000000700UL
#define UVH_IPI_INT_DESTMODE_MASK			0x0000000000000800UL
#define UVH_IPI_INT_APIC_ID_MASK			0x0000ffffffff0000UL
#define UVH_IPI_INT_SEND_MASK				0x8000000000000000UL

union uvh_ipi_int_u {
	unsigned long	v;
	struct uvh_ipi_int_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	delivery_mode:3;		/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	rsvd_12_15:4;
		unsigned long	apic_id:32;			/* RW */
		unsigned long	rsvd_48_62:15;
		unsigned long	send:1;				/* WP */
	} s;
};

/* ========================================================================= */
/*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
/* ========================================================================= */
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL

union uvh_lb_bau_intd_payload_queue_first_u {
	unsigned long	v;
	struct uvh_lb_bau_intd_payload_queue_first_s {
		unsigned long	rsvd_0_3:4;
		unsigned long	address:39;			/* RW */
		unsigned long	rsvd_43_48:6;
		unsigned long	node_id:14;			/* RW */
		unsigned long	rsvd_63:1;
	} s;
};

/* ========================================================================= */
/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
/* ========================================================================= */
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT	4
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK	0x000007fffffffff0UL

union uvh_lb_bau_intd_payload_queue_last_u {
	unsigned long	v;
	struct uvh_lb_bau_intd_payload_queue_last_s {
		unsigned long	rsvd_0_3:4;
		unsigned long	address:39;			/* RW */
		unsigned long	rsvd_43_63:21;
	} s;
};

/* ========================================================================= */
/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
/* ========================================================================= */
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0

#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT	4
#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK	0x000007fffffffff0UL

union uvh_lb_bau_intd_payload_queue_tail_u {
	unsigned long	v;
	struct uvh_lb_bau_intd_payload_queue_tail_s {
		unsigned long	rsvd_0_3:4;
		unsigned long	address:39;			/* RW */
		unsigned long	rsvd_43_63:21;
	} s;
};

/* ========================================================================= */
/*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
/* ========================================================================= */
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68

#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL

union uvh_lb_bau_intd_software_acknowledge_u {
	unsigned long	v;
	struct uvh_lb_bau_intd_software_acknowledge_s {
		unsigned long	pending_0:1;			/* RW, W1C */
		unsigned long	pending_1:1;			/* RW, W1C */
		unsigned long	pending_2:1;			/* RW, W1C */
		unsigned long	pending_3:1;			/* RW, W1C */
		unsigned long	pending_4:1;			/* RW, W1C */
		unsigned long	pending_5:1;			/* RW, W1C */
		unsigned long	pending_6:1;			/* RW, W1C */
		unsigned long	pending_7:1;			/* RW, W1C */
		unsigned long	timeout_0:1;			/* RW, W1C */
		unsigned long	timeout_1:1;			/* RW, W1C */
		unsigned long	timeout_2:1;			/* RW, W1C */
		unsigned long	timeout_3:1;			/* RW, W1C */
		unsigned long	timeout_4:1;			/* RW, W1C */
		unsigned long	timeout_5:1;			/* RW, W1C */
		unsigned long	timeout_6:1;			/* RW, W1C */
		unsigned long	timeout_7:1;			/* RW, W1C */
		unsigned long	rsvd_16_63:48;
	} s;
};

/* ========================================================================= */
/*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
/* ========================================================================= */
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70


/* ========================================================================= */
/*                         UVH_LB_BAU_MISC_CONTROL                           */
/* ========================================================================= */
#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
#define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
#define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
#define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
#define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL
#define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL
#define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL

#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL

#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL

#define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
#define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
#define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
#define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
#define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
#define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
#define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
#define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL

#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL

#define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
#define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
#define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
#define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
#define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37
#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
#define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
#define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
#define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
#define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
#define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
#define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL
#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
#define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL

union uvh_lb_bau_misc_control_u {
	unsigned long	v;
	struct uvh_lb_bau_misc_control_s {
		unsigned long	rejection_delay:8;		/* RW */
		unsigned long	apic_mode:1;			/* RW */
		unsigned long	force_broadcast:1;		/* RW */
		unsigned long	force_lock_nop:1;		/* RW */
		unsigned long	qpi_agent_presence_vector:3;	/* RW */
		unsigned long	descriptor_fetch_mode:1;	/* RW */
		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
		unsigned long	enable_dual_mapping_mode:1;	/* RW */
		unsigned long	vga_io_port_decode_enable:1;	/* RW */
		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
		unsigned long	suppress_dest_registration:1;	/* RW */
		unsigned long	programmed_initial_priority:3;	/* RW */
		unsigned long	use_incoming_priority:1;	/* RW */
		unsigned long	enable_programmed_initial_priority:1;/* RW */
		unsigned long	rsvd_29_47:19;
		unsigned long	fun:16;				/* RW */
	} s;
	struct uv1h_lb_bau_misc_control_s {
		unsigned long	rejection_delay:8;		/* RW */
		unsigned long	apic_mode:1;			/* RW */
		unsigned long	force_broadcast:1;		/* RW */
		unsigned long	force_lock_nop:1;		/* RW */
		unsigned long	qpi_agent_presence_vector:3;	/* RW */
		unsigned long	descriptor_fetch_mode:1;	/* RW */
		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
		unsigned long	enable_dual_mapping_mode:1;	/* RW */
		unsigned long	vga_io_port_decode_enable:1;	/* RW */
		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
		unsigned long	suppress_dest_registration:1;	/* RW */
		unsigned long	programmed_initial_priority:3;	/* RW */
		unsigned long	use_incoming_priority:1;	/* RW */
		unsigned long	enable_programmed_initial_priority:1;/* RW */
		unsigned long	rsvd_29_47:19;
		unsigned long	fun:16;				/* RW */
	} s1;
	struct uvxh_lb_bau_misc_control_s {
		unsigned long	rejection_delay:8;		/* RW */
		unsigned long	apic_mode:1;			/* RW */
		unsigned long	force_broadcast:1;		/* RW */
		unsigned long	force_lock_nop:1;		/* RW */
		unsigned long	qpi_agent_presence_vector:3;	/* RW */
		unsigned long	descriptor_fetch_mode:1;	/* RW */
		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
		unsigned long	enable_dual_mapping_mode:1;	/* RW */
		unsigned long	vga_io_port_decode_enable:1;	/* RW */
		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
		unsigned long	suppress_dest_registration:1;	/* RW */
		unsigned long	programmed_initial_priority:3;	/* RW */
		unsigned long	use_incoming_priority:1;	/* RW */
		unsigned long	enable_programmed_initial_priority:1;/* RW */
		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
		unsigned long	apic_mode_status:1;		/* RO */
		unsigned long	suppress_interrupts_to_self:1;	/* RW */
		unsigned long	enable_lock_based_system_flush:1;/* RW */
		unsigned long	enable_extended_sb_status:1;	/* RW */
		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
		unsigned long	use_legacy_descriptor_formats:1;/* RW */
		unsigned long	rsvd_36_47:12;
		unsigned long	fun:16;				/* RW */
	} sx;
	struct uv2h_lb_bau_misc_control_s {
		unsigned long	rejection_delay:8;		/* RW */
		unsigned long	apic_mode:1;			/* RW */
		unsigned long	force_broadcast:1;		/* RW */
		unsigned long	force_lock_nop:1;		/* RW */
		unsigned long	qpi_agent_presence_vector:3;	/* RW */
		unsigned long	descriptor_fetch_mode:1;	/* RW */
		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
		unsigned long	enable_dual_mapping_mode:1;	/* RW */
		unsigned long	vga_io_port_decode_enable:1;	/* RW */
		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
		unsigned long	suppress_dest_registration:1;	/* RW */
		unsigned long	programmed_initial_priority:3;	/* RW */
		unsigned long	use_incoming_priority:1;	/* RW */
		unsigned long	enable_programmed_initial_priority:1;/* RW */
		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
		unsigned long	apic_mode_status:1;		/* RO */
		unsigned long	suppress_interrupts_to_self:1;	/* RW */
		unsigned long	enable_lock_based_system_flush:1;/* RW */
		unsigned long	enable_extended_sb_status:1;	/* RW */
		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
		unsigned long	use_legacy_descriptor_formats:1;/* RW */
		unsigned long	rsvd_36_47:12;
		unsigned long	fun:16;				/* RW */
	} s2;
	struct uv3h_lb_bau_misc_control_s {
		unsigned long	rejection_delay:8;		/* RW */
		unsigned long	apic_mode:1;			/* RW */
		unsigned long	force_broadcast:1;		/* RW */
		unsigned long	force_lock_nop:1;		/* RW */
		unsigned long	qpi_agent_presence_vector:3;	/* RW */
		unsigned long	descriptor_fetch_mode:1;	/* RW */
		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
		unsigned long	enable_dual_mapping_mode:1;	/* RW */
		unsigned long	vga_io_port_decode_enable:1;	/* RW */
		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
		unsigned long	suppress_dest_registration:1;	/* RW */
		unsigned long	programmed_initial_priority:3;	/* RW */
		unsigned long	use_incoming_priority:1;	/* RW */
		unsigned long	enable_programmed_initial_priority:1;/* RW */
		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
		unsigned long	apic_mode_status:1;		/* RO */
		unsigned long	suppress_interrupts_to_self:1;	/* RW */
		unsigned long	enable_lock_based_system_flush:1;/* RW */
		unsigned long	enable_extended_sb_status:1;	/* RW */
		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
		unsigned long	use_legacy_descriptor_formats:1;/* RW */
		unsigned long	suppress_quiesce_msgs_to_qpi:1;	/* RW */
		unsigned long	enable_intd_prefetch_hint:1;	/* RW */
		unsigned long	thread_kill_timebase:8;		/* RW */
		unsigned long	rsvd_46_47:2;
		unsigned long	fun:16;				/* RW */
	} s3;
};

/* ========================================================================= */
/*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
/* ========================================================================= */
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8

#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT	0
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT	62
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT	63
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK	0x000000000000003fUL
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK	0x4000000000000000UL
#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK	0x8000000000000000UL

union uvh_lb_bau_sb_activation_control_u {
	unsigned long	v;
	struct uvh_lb_bau_sb_activation_control_s {
		unsigned long	index:6;			/* RW */
		unsigned long	rsvd_6_61:56;
		unsigned long	push:1;				/* WP */
		unsigned long	init:1;				/* WP */
	} s;
};

/* ========================================================================= */
/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
/* ========================================================================= */
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT	0
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK	0xffffffffffffffffUL

union uvh_lb_bau_sb_activation_status_0_u {
	unsigned long	v;
	struct uvh_lb_bau_sb_activation_status_0_s {
		unsigned long	status:64;			/* RW */
	} s;
};

/* ========================================================================= */
/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
/* ========================================================================= */
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8

#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT	0
#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK	0xffffffffffffffffUL

union uvh_lb_bau_sb_activation_status_1_u {
	unsigned long	v;
	struct uvh_lb_bau_sb_activation_status_1_s {
		unsigned long	status:64;			/* RW */
	} s;
};

/* ========================================================================= */
/*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
/* ========================================================================= */
#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0

#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT	12
#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK	0x000007fffffff000UL
#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL

union uvh_lb_bau_sb_descriptor_base_u {
	unsigned long	v;
	struct uvh_lb_bau_sb_descriptor_base_s {
		unsigned long	rsvd_0_11:12;
		unsigned long	page_address:31;		/* RW */
		unsigned long	rsvd_43_48:6;
		unsigned long	node_id:14;			/* RW */
		unsigned long	rsvd_63:1;
	} s;
};

/* ========================================================================= */
/*                               UVH_NODE_ID                                 */
/* ========================================================================= */
#define UVH_NODE_ID 0x0UL
#define UV1H_NODE_ID 0x0UL
#define UV2H_NODE_ID 0x0UL
#define UV3H_NODE_ID 0x0UL

#define UVH_NODE_ID_FORCE1_SHFT				0
#define UVH_NODE_ID_MANUFACTURER_SHFT			1
#define UVH_NODE_ID_PART_NUMBER_SHFT			12
#define UVH_NODE_ID_REVISION_SHFT			28
#define UVH_NODE_ID_NODE_ID_SHFT			32
#define UVH_NODE_ID_FORCE1_MASK				0x0000000000000001UL
#define UVH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
#define UVH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
#define UVH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
#define UVH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL

#define UV1H_NODE_ID_FORCE1_SHFT			0
#define UV1H_NODE_ID_MANUFACTURER_SHFT			1
#define UV1H_NODE_ID_PART_NUMBER_SHFT			12
#define UV1H_NODE_ID_REVISION_SHFT			28
#define UV1H_NODE_ID_NODE_ID_SHFT			32
#define UV1H_NODE_ID_NODES_PER_BIT_SHFT			48
#define UV1H_NODE_ID_NI_PORT_SHFT			56
#define UV1H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
#define UV1H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
#define UV1H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
#define UV1H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
#define UV1H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
#define UV1H_NODE_ID_NODES_PER_BIT_MASK			0x007f000000000000UL
#define UV1H_NODE_ID_NI_PORT_MASK			0x0f00000000000000UL

#define UVXH_NODE_ID_FORCE1_SHFT			0
#define UVXH_NODE_ID_MANUFACTURER_SHFT			1
#define UVXH_NODE_ID_PART_NUMBER_SHFT			12
#define UVXH_NODE_ID_REVISION_SHFT			28
#define UVXH_NODE_ID_NODE_ID_SHFT			32
#define UVXH_NODE_ID_NODES_PER_BIT_SHFT			50
#define UVXH_NODE_ID_NI_PORT_SHFT			57
#define UVXH_NODE_ID_FORCE1_MASK			0x0000000000000001UL
#define UVXH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
#define UVXH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
#define UVXH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
#define UVXH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
#define UVXH_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
#define UVXH_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL

#define UV2H_NODE_ID_FORCE1_SHFT			0
#define UV2H_NODE_ID_MANUFACTURER_SHFT			1
#define UV2H_NODE_ID_PART_NUMBER_SHFT			12
#define UV2H_NODE_ID_REVISION_SHFT			28
#define UV2H_NODE_ID_NODE_ID_SHFT			32
#define UV2H_NODE_ID_NODES_PER_BIT_SHFT			50
#define UV2H_NODE_ID_NI_PORT_SHFT			57
#define UV2H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
#define UV2H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
#define UV2H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
#define UV2H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
#define UV2H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
#define UV2H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
#define UV2H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL

#define UV3H_NODE_ID_FORCE1_SHFT			0
#define UV3H_NODE_ID_MANUFACTURER_SHFT			1
#define UV3H_NODE_ID_PART_NUMBER_SHFT			12
#define UV3H_NODE_ID_REVISION_SHFT			28
#define UV3H_NODE_ID_NODE_ID_SHFT			32
#define UV3H_NODE_ID_ROUTER_SELECT_SHFT			48
#define UV3H_NODE_ID_RESERVED_2_SHFT			49
#define UV3H_NODE_ID_NODES_PER_BIT_SHFT			50
#define UV3H_NODE_ID_NI_PORT_SHFT			57
#define UV3H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
#define UV3H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
#define UV3H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
#define UV3H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
#define UV3H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
#define UV3H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
#define UV3H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
#define UV3H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
#define UV3H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL

union uvh_node_id_u {
	unsigned long	v;
	struct uvh_node_id_s {
		unsigned long	force1:1;			/* RO */
		unsigned long	manufacturer:11;		/* RO */
		unsigned long	part_number:16;			/* RO */
		unsigned long	revision:4;			/* RO */
		unsigned long	node_id:15;			/* RW */
		unsigned long	rsvd_47_63:17;
	} s;
	struct uv1h_node_id_s {
		unsigned long	force1:1;			/* RO */
		unsigned long	manufacturer:11;		/* RO */
		unsigned long	part_number:16;			/* RO */
		unsigned long	revision:4;			/* RO */
		unsigned long	node_id:15;			/* RW */
		unsigned long	rsvd_47:1;
		unsigned long	nodes_per_bit:7;		/* RW */
		unsigned long	rsvd_55:1;
		unsigned long	ni_port:4;			/* RO */
		unsigned long	rsvd_60_63:4;
	} s1;
	struct uvxh_node_id_s {
		unsigned long	force1:1;			/* RO */
		unsigned long	manufacturer:11;		/* RO */
		unsigned long	part_number:16;			/* RO */
		unsigned long	revision:4;			/* RO */
		unsigned long	node_id:15;			/* RW */
		unsigned long	rsvd_47_49:3;
		unsigned long	nodes_per_bit:7;		/* RO */
		unsigned long	ni_port:5;			/* RO */
		unsigned long	rsvd_62_63:2;
	} sx;
	struct uv2h_node_id_s {
		unsigned long	force1:1;			/* RO */
		unsigned long	manufacturer:11;		/* RO */
		unsigned long	part_number:16;			/* RO */
		unsigned long	revision:4;			/* RO */
		unsigned long	node_id:15;			/* RW */
		unsigned long	rsvd_47_49:3;
		unsigned long	nodes_per_bit:7;		/* RO */
		unsigned long	ni_port:5;			/* RO */
		unsigned long	rsvd_62_63:2;
	} s2;
	struct uv3h_node_id_s {
		unsigned long	force1:1;			/* RO */
		unsigned long	manufacturer:11;		/* RO */
		unsigned long	part_number:16;			/* RO */
		unsigned long	revision:4;			/* RO */
		unsigned long	node_id:15;			/* RW */
		unsigned long	rsvd_47:1;
		unsigned long	router_select:1;		/* RO */
		unsigned long	rsvd_49:1;
		unsigned long	nodes_per_bit:7;		/* RO */
		unsigned long	ni_port:5;			/* RO */
		unsigned long	rsvd_62_63:2;
	} s3;
};

/* ========================================================================= */
/*                          UVH_NODE_PRESENT_TABLE                           */
/* ========================================================================= */
#define UVH_NODE_PRESENT_TABLE 0x1400UL
#define UVH_NODE_PRESENT_TABLE_DEPTH 16

#define UVH_NODE_PRESENT_TABLE_NODES_SHFT		0
#define UVH_NODE_PRESENT_TABLE_NODES_MASK		0xffffffffffffffffUL

union uvh_node_present_table_u {
	unsigned long	v;
	struct uvh_node_present_table_s {
		unsigned long	nodes:64;			/* RW */
	} s;
};

/* ========================================================================= */
/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL

union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	base:8;				/* RW */
		unsigned long	rsvd_32_47:16;
		unsigned long	m_alias:5;			/* RW */
		unsigned long	rsvd_53_62:10;
		unsigned long	enable:1;			/* RW */
	} s;
};

/* ========================================================================= */
/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL

union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	base:8;				/* RW */
		unsigned long	rsvd_32_47:16;
		unsigned long	m_alias:5;			/* RW */
		unsigned long	rsvd_53_62:10;
		unsigned long	enable:1;			/* RW */
	} s;
};

/* ========================================================================= */
/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL

#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL

union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	base:8;				/* RW */
		unsigned long	rsvd_32_47:16;
		unsigned long	m_alias:5;			/* RW */
		unsigned long	rsvd_53_62:10;
		unsigned long	enable:1;			/* RW */
	} s;
};

/* ========================================================================= */
/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL

#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL

union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	dest_base:22;			/* RW */
		unsigned long	rsvd_46_63:18;
	} s;
};

/* ========================================================================= */
/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL

#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL

union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	dest_base:22;			/* RW */
		unsigned long	rsvd_46_63:18;
	} s;
};

/* ========================================================================= */
/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
/* ========================================================================= */
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL

#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL

union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
		unsigned long	rsvd_0_23:24;
		unsigned long	dest_base:22;			/* RW */
		unsigned long	rsvd_46_63:18;
	} s;
};

/* ========================================================================= */
/*                          UVH_RH_GAM_CONFIG_MMR                            */
/* ========================================================================= */
#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
#define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
#define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
#define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL

#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL

#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT		12
#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK		0x0000000000001000UL

#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL

#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL

#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL

union uvh_rh_gam_config_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_config_mmr_s {
		unsigned long	m_skt:6;			/* RW */
		unsigned long	n_skt:4;			/* RW */
		unsigned long	rsvd_10_63:54;
	} s;
	struct uv1h_rh_gam_config_mmr_s {
		unsigned long	m_skt:6;			/* RW */
		unsigned long	n_skt:4;			/* RW */
		unsigned long	rsvd_10_11:2;
		unsigned long	mmiol_cfg:1;			/* RW */
		unsigned long	rsvd_13_63:51;
	} s1;
	struct uvxh_rh_gam_config_mmr_s {
		unsigned long	m_skt:6;			/* RW */
		unsigned long	n_skt:4;			/* RW */
		unsigned long	rsvd_10_63:54;
	} sx;
	struct uv2h_rh_gam_config_mmr_s {
		unsigned long	m_skt:6;			/* RW */
		unsigned long	n_skt:4;			/* RW */
		unsigned long	rsvd_10_63:54;
	} s2;
	struct uv3h_rh_gam_config_mmr_s {
		unsigned long	m_skt:6;			/* RW */
		unsigned long	n_skt:4;			/* RW */
		unsigned long	rsvd_10_63:54;
	} s3;
};

/* ========================================================================= */
/*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
/* ========================================================================= */
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL

#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT	48
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK	0x0001000000000000UL
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT	62
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK	0x4000000000000000UL
#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

union uvh_rh_gam_gru_overlay_config_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_gru_overlay_config_mmr_s {
		unsigned long	rsvd_0_27:28;
		unsigned long	base:18;			/* RW */
		unsigned long	rsvd_46_51:6;
		unsigned long	n_gru:4;			/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s;
	struct uv1h_rh_gam_gru_overlay_config_mmr_s {
		unsigned long	rsvd_0_27:28;
		unsigned long	base:18;			/* RW */
		unsigned long	rsvd_46_47:2;
		unsigned long	gr4:1;				/* RW */
		unsigned long	rsvd_49_51:3;
		unsigned long	n_gru:4;			/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s1;
	struct uvxh_rh_gam_gru_overlay_config_mmr_s {
		unsigned long	rsvd_0_27:28;
		unsigned long	base:18;			/* RW */
		unsigned long	rsvd_46_51:6;
		unsigned long	n_gru:4;			/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} sx;
	struct uv2h_rh_gam_gru_overlay_config_mmr_s {
		unsigned long	rsvd_0_27:28;
		unsigned long	base:18;			/* RW */
		unsigned long	rsvd_46_51:6;
		unsigned long	n_gru:4;			/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s2;
	struct uv3h_rh_gam_gru_overlay_config_mmr_s {
		unsigned long	rsvd_0_27:28;
		unsigned long	base:18;			/* RW */
		unsigned long	rsvd_46_51:6;
		unsigned long	n_gru:4;			/* RW */
		unsigned long	rsvd_56_61:6;
		unsigned long	mode:1;				/* RW */
		unsigned long	enable:1;			/* RW */
	} s3;
};

/* ========================================================================= */
/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
/* ========================================================================= */
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL

#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	30
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003fffc0000000UL
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	27
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff8000000UL
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL

union uvh_rh_gam_mmioh_overlay_config_mmr_u {
	unsigned long	v;
	struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
		unsigned long	rsvd_0_29:30;
		unsigned long	base:16;			/* RW */
		unsigned long	m_io:6;				/* RW */
		unsigned long	n_io:4;				/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s1;
	struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
		unsigned long	rsvd_0_26:27;
		unsigned long	base:19;			/* RW */
		unsigned long	m_io:6;				/* RW */
		unsigned long	n_io:4;				/* RW */
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s2;
};

/* ========================================================================= */
/*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
/* ========================================================================= */
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL

#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL

union uvh_rh_gam_mmr_overlay_config_mmr_u {
	unsigned long	v;
	struct uvh_rh_gam_mmr_overlay_config_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	rsvd_46_62:17;
		unsigned long	enable:1;			/* RW */
	} s;
	struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	dual_hub:1;			/* RW */
		unsigned long	rsvd_47_62:16;
		unsigned long	enable:1;			/* RW */
	} s1;
	struct uvxh_rh_gam_mmr_overlay_config_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	rsvd_46_62:17;
		unsigned long	enable:1;			/* RW */
	} sx;
	struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	rsvd_46_62:17;
		unsigned long	enable:1;			/* RW */
	} s2;
	struct uv3h_rh_gam_mmr_overlay_config_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	rsvd_46_62:17;
		unsigned long	enable:1;			/* RW */
	} s3;
};

/* ========================================================================= */
/*                                 UVH_RTC                                   */
/* ========================================================================= */
#define UVH_RTC 0x340000UL

#define UVH_RTC_REAL_TIME_CLOCK_SHFT			0
#define UVH_RTC_REAL_TIME_CLOCK_MASK			0x00ffffffffffffffUL

union uvh_rtc_u {
	unsigned long	v;
	struct uvh_rtc_s {
		unsigned long	real_time_clock:56;		/* RW */
		unsigned long	rsvd_56_63:8;
	} s;
};

/* ========================================================================= */
/*                           UVH_RTC1_INT_CONFIG                             */
/* ========================================================================= */
#define UVH_RTC1_INT_CONFIG 0x615c0UL

#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT			0
#define UVH_RTC1_INT_CONFIG_DM_SHFT			8
#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT		11
#define UVH_RTC1_INT_CONFIG_STATUS_SHFT			12
#define UVH_RTC1_INT_CONFIG_P_SHFT			13
#define UVH_RTC1_INT_CONFIG_T_SHFT			15
#define UVH_RTC1_INT_CONFIG_M_SHFT			16
#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT		32
#define UVH_RTC1_INT_CONFIG_VECTOR_MASK			0x00000000000000ffUL
#define UVH_RTC1_INT_CONFIG_DM_MASK			0x0000000000000700UL
#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK		0x0000000000000800UL
#define UVH_RTC1_INT_CONFIG_STATUS_MASK			0x0000000000001000UL
#define UVH_RTC1_INT_CONFIG_P_MASK			0x0000000000002000UL
#define UVH_RTC1_INT_CONFIG_T_MASK			0x0000000000008000UL
#define UVH_RTC1_INT_CONFIG_M_MASK			0x0000000000010000UL
#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK		0xffffffff00000000UL

union uvh_rtc1_int_config_u {
	unsigned long	v;
	struct uvh_rtc1_int_config_s {
		unsigned long	vector_:8;			/* RW */
		unsigned long	dm:3;				/* RW */
		unsigned long	destmode:1;			/* RW */
		unsigned long	status:1;			/* RO */
		unsigned long	p:1;				/* RO */
		unsigned long	rsvd_14:1;
		unsigned long	t:1;				/* RO */
		unsigned long	m:1;				/* RW */
		unsigned long	rsvd_17_31:15;
		unsigned long	apic_id:32;			/* RW */
	} s;
};

/* ========================================================================= */
/*                               UVH_SCRATCH5                                */
/* ========================================================================= */
#define UVH_SCRATCH5 0x2d0200UL
#define UVH_SCRATCH5_32 0x778

#define UVH_SCRATCH5_SCRATCH5_SHFT			0
#define UVH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL

union uvh_scratch5_u {
	unsigned long	v;
	struct uvh_scratch5_s {
		unsigned long	scratch5:64;			/* RW, W1CS */
	} s;
};

/* ========================================================================= */
/*                          UVXH_EVENT_OCCURRED2                             */
/* ========================================================================= */
#define UVXH_EVENT_OCCURRED2 0x70100UL
#define UVXH_EVENT_OCCURRED2_32 0xb68

#define UVXH_EVENT_OCCURRED2_RTC_0_SHFT			0
#define UVXH_EVENT_OCCURRED2_RTC_1_SHFT			1
#define UVXH_EVENT_OCCURRED2_RTC_2_SHFT			2
#define UVXH_EVENT_OCCURRED2_RTC_3_SHFT			3
#define UVXH_EVENT_OCCURRED2_RTC_4_SHFT			4
#define UVXH_EVENT_OCCURRED2_RTC_5_SHFT			5
#define UVXH_EVENT_OCCURRED2_RTC_6_SHFT			6
#define UVXH_EVENT_OCCURRED2_RTC_7_SHFT			7
#define UVXH_EVENT_OCCURRED2_RTC_8_SHFT			8
#define UVXH_EVENT_OCCURRED2_RTC_9_SHFT			9
#define UVXH_EVENT_OCCURRED2_RTC_10_SHFT		10
#define UVXH_EVENT_OCCURRED2_RTC_11_SHFT		11
#define UVXH_EVENT_OCCURRED2_RTC_12_SHFT		12
#define UVXH_EVENT_OCCURRED2_RTC_13_SHFT		13
#define UVXH_EVENT_OCCURRED2_RTC_14_SHFT		14
#define UVXH_EVENT_OCCURRED2_RTC_15_SHFT		15
#define UVXH_EVENT_OCCURRED2_RTC_16_SHFT		16
#define UVXH_EVENT_OCCURRED2_RTC_17_SHFT		17
#define UVXH_EVENT_OCCURRED2_RTC_18_SHFT		18
#define UVXH_EVENT_OCCURRED2_RTC_19_SHFT		19
#define UVXH_EVENT_OCCURRED2_RTC_20_SHFT		20
#define UVXH_EVENT_OCCURRED2_RTC_21_SHFT		21
#define UVXH_EVENT_OCCURRED2_RTC_22_SHFT		22
#define UVXH_EVENT_OCCURRED2_RTC_23_SHFT		23
#define UVXH_EVENT_OCCURRED2_RTC_24_SHFT		24
#define UVXH_EVENT_OCCURRED2_RTC_25_SHFT		25
#define UVXH_EVENT_OCCURRED2_RTC_26_SHFT		26
#define UVXH_EVENT_OCCURRED2_RTC_27_SHFT		27
#define UVXH_EVENT_OCCURRED2_RTC_28_SHFT		28
#define UVXH_EVENT_OCCURRED2_RTC_29_SHFT		29
#define UVXH_EVENT_OCCURRED2_RTC_30_SHFT		30
#define UVXH_EVENT_OCCURRED2_RTC_31_SHFT		31
#define UVXH_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
#define UVXH_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
#define UVXH_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
#define UVXH_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
#define UVXH_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
#define UVXH_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
#define UVXH_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
#define UVXH_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
#define UVXH_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
#define UVXH_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
#define UVXH_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
#define UVXH_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
#define UVXH_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
#define UVXH_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
#define UVXH_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
#define UVXH_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
#define UVXH_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
#define UVXH_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
#define UVXH_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
#define UVXH_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
#define UVXH_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
#define UVXH_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
#define UVXH_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
#define UVXH_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
#define UVXH_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
#define UVXH_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
#define UVXH_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
#define UVXH_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
#define UVXH_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
#define UVXH_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
#define UVXH_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
#define UVXH_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL

union uvxh_event_occurred2_u {
	unsigned long	v;
	struct uvxh_event_occurred2_s {
		unsigned long	rtc_0:1;			/* RW */
		unsigned long	rtc_1:1;			/* RW */
		unsigned long	rtc_2:1;			/* RW */
		unsigned long	rtc_3:1;			/* RW */
		unsigned long	rtc_4:1;			/* RW */
		unsigned long	rtc_5:1;			/* RW */
		unsigned long	rtc_6:1;			/* RW */
		unsigned long	rtc_7:1;			/* RW */
		unsigned long	rtc_8:1;			/* RW */
		unsigned long	rtc_9:1;			/* RW */
		unsigned long	rtc_10:1;			/* RW */
		unsigned long	rtc_11:1;			/* RW */
		unsigned long	rtc_12:1;			/* RW */
		unsigned long	rtc_13:1;			/* RW */
		unsigned long	rtc_14:1;			/* RW */
		unsigned long	rtc_15:1;			/* RW */
		unsigned long	rtc_16:1;			/* RW */
		unsigned long	rtc_17:1;			/* RW */
		unsigned long	rtc_18:1;			/* RW */
		unsigned long	rtc_19:1;			/* RW */
		unsigned long	rtc_20:1;			/* RW */
		unsigned long	rtc_21:1;			/* RW */
		unsigned long	rtc_22:1;			/* RW */
		unsigned long	rtc_23:1;			/* RW */
		unsigned long	rtc_24:1;			/* RW */
		unsigned long	rtc_25:1;			/* RW */
		unsigned long	rtc_26:1;			/* RW */
		unsigned long	rtc_27:1;			/* RW */
		unsigned long	rtc_28:1;			/* RW */
		unsigned long	rtc_29:1;			/* RW */
		unsigned long	rtc_30:1;			/* RW */
		unsigned long	rtc_31:1;			/* RW */
		unsigned long	rsvd_32_63:32;
	} sx;
};

/* ========================================================================= */
/*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
/* ========================================================================= */
#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
#define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70


/* ========================================================================= */
/*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
/* ========================================================================= */
#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL
#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL

#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL

#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL

#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL

union uvxh_lb_bau_sb_activation_status_2_u {
	unsigned long	v;
	struct uvxh_lb_bau_sb_activation_status_2_s {
		unsigned long	aux_error:64;			/* RW */
	} sx;
	struct uv2h_lb_bau_sb_activation_status_2_s {
		unsigned long	aux_error:64;			/* RW */
	} s2;
	struct uv3h_lb_bau_sb_activation_status_2_s {
		unsigned long	aux_error:64;			/* RW */
	} s3;
};

/* ========================================================================= */
/*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
/* ========================================================================= */
#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK		0x320130UL
#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32		0x9f0

#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL

union uv1h_lb_target_physical_apic_id_mask_u {
	unsigned long	v;
	struct uv1h_lb_target_physical_apic_id_mask_s {
		unsigned long	bit_enables:32;			/* RW */
		unsigned long	rsvd_32_63:32;
	} s1;
};

/* ========================================================================= */
/*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                   */
/* ========================================================================= */
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR		0x1603000UL

#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT	26
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT	46
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK	0x00003ffffc000000UL
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK	0x000fc00000000000UL
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL

union uv3h_rh_gam_mmioh_overlay_config0_mmr_u {
	unsigned long	v;
	struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	m_io:6;				/* RW */
		unsigned long	n_io:4;
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s3;
};

/* ========================================================================= */
/*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR                   */
/* ========================================================================= */
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR		0x1604000UL

#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT	26
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT	46
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK	0x00003ffffc000000UL
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK	0x000fc00000000000UL
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL

union uv3h_rh_gam_mmioh_overlay_config1_mmr_u {
	unsigned long	v;
	struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
		unsigned long	rsvd_0_25:26;
		unsigned long	base:20;			/* RW */
		unsigned long	m_io:6;				/* RW */
		unsigned long	n_io:4;
		unsigned long	rsvd_56_62:7;
		unsigned long	enable:1;			/* RW */
	} s3;
};

/* ========================================================================= */
/*                  UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR                   */
/* ========================================================================= */
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR		0x1603800UL
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH	128

#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL

union uv3h_rh_gam_mmioh_redirect_config0_mmr_u {
	unsigned long	v;
	struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
		unsigned long	nasid:15;			/* RW */
		unsigned long	rsvd_15_63:49;
	} s3;
};

/* ========================================================================= */
/*                  UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR                   */
/* ========================================================================= */
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR		0x1604800UL
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH	128

#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL

union uv3h_rh_gam_mmioh_redirect_config1_mmr_u {
	unsigned long	v;
	struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
		unsigned long	nasid:15;			/* RW */
		unsigned long	rsvd_15_63:49;
	} s3;
};


#endif /* _ASM_X86_UV_UV_MMRS_H */