1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DPU_HW_UTIL_H
#define _DPU_HW_UTIL_H
#include <linux/io.h>
#include <linux/slab.h>
#include "dpu_hw_mdss.h"
#define REG_MASK(n) ((BIT(n)) - 1)
/*
* This is the common struct maintained by each sub block
* for mapping the register offsets in this block to the
* absoulute IO address
* @base_off: mdp register mapped offset
* @blk_off: pipe offset relative to mdss offset
* @length length of register block offset
* @xin_id xin id
* @hwversion mdss hw version number
*/
struct dpu_hw_blk_reg_map {
void __iomem *base_off;
u32 blk_off;
u32 length;
u32 xin_id;
u32 hwversion;
u32 log_mask;
};
/**
* struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
* @enable: detail enhancer enable/disable
* @sharpen_level1: sharpening strength for noise
* @sharpen_level2: sharpening strength for signal
* @ clip: clip shift
* @ limit: limit value
* @ thr_quiet: quiet threshold
* @ thr_dieout: dieout threshold
* @ thr_high: low threshold
* @ thr_high: high threshold
* @ prec_shift: precision shift
* @ adjust_a: A-coefficients for mapping curve
* @ adjust_b: B-coefficients for mapping curve
* @ adjust_c: C-coefficients for mapping curve
*/
struct dpu_hw_scaler3_de_cfg {
u32 enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[DPU_MAX_DE_CURVES];
int16_t adjust_b[DPU_MAX_DE_CURVES];
int16_t adjust_c[DPU_MAX_DE_CURVES];
};
/**
* struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
* @enable: scaler enable
* @dir_en: direction detection block enable
* @ init_phase_x: horizontal initial phase
* @ phase_step_x: horizontal phase step
* @ init_phase_y: vertical initial phase
* @ phase_step_y: vertical phase step
* @ preload_x: horizontal preload value
* @ preload_y: vertical preload value
* @ src_width: source width
* @ src_height: source height
* @ dst_width: destination width
* @ dst_height: destination height
* @ y_rgb_filter_cfg: y/rgb plane filter configuration
* @ uv_filter_cfg: uv plane filter configuration
* @ alpha_filter_cfg: alpha filter configuration
* @ blend_cfg: blend coefficients configuration
* @ lut_flag: scaler LUT update flags
* 0x1 swap LUT bank
* 0x2 update 2D filter LUT
* 0x4 update y circular filter LUT
* 0x8 update uv circular filter LUT
* 0x10 update y separable filter LUT
* 0x20 update uv separable filter LUT
* @ dir_lut_idx: 2D filter LUT index
* @ y_rgb_cir_lut_idx: y circular filter LUT index
* @ uv_cir_lut_idx: uv circular filter LUT index
* @ y_rgb_sep_lut_idx: y circular filter LUT index
* @ uv_sep_lut_idx: uv separable filter LUT index
* @ dir_lut: pointer to 2D LUT
* @ cir_lut: pointer to circular filter LUT
* @ sep_lut: pointer to separable filter LUT
* @ de: detail enhancer configuration
*/
struct dpu_hw_scaler3_cfg {
u32 enable;
u32 dir_en;
int32_t init_phase_x[DPU_MAX_PLANES];
int32_t phase_step_x[DPU_MAX_PLANES];
int32_t init_phase_y[DPU_MAX_PLANES];
int32_t phase_step_y[DPU_MAX_PLANES];
u32 preload_x[DPU_MAX_PLANES];
u32 preload_y[DPU_MAX_PLANES];
u32 src_width[DPU_MAX_PLANES];
u32 src_height[DPU_MAX_PLANES];
u32 dst_width;
u32 dst_height;
u32 y_rgb_filter_cfg;
u32 uv_filter_cfg;
u32 alpha_filter_cfg;
u32 blend_cfg;
u32 lut_flag;
u32 dir_lut_idx;
u32 y_rgb_cir_lut_idx;
u32 uv_cir_lut_idx;
u32 y_rgb_sep_lut_idx;
u32 uv_sep_lut_idx;
u32 *dir_lut;
size_t dir_len;
u32 *cir_lut;
size_t cir_len;
u32 *sep_lut;
size_t sep_len;
/*
* Detail enhancer settings
*/
struct dpu_hw_scaler3_de_cfg de;
};
/**
* struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
* @num_ext_pxls_lr: Number of total horizontal pixels
* @num_ext_pxls_tb: Number of total vertical lines
* @left_ftch: Number of extra pixels to overfetch from left
* @right_ftch: Number of extra pixels to overfetch from right
* @top_ftch: Number of extra lines to overfetch from top
* @btm_ftch: Number of extra lines to overfetch from bottom
* @left_rpt: Number of extra pixels to repeat from left
* @right_rpt: Number of extra pixels to repeat from right
* @top_rpt: Number of extra lines to repeat from top
* @btm_rpt: Number of extra lines to repeat from bottom
*/
struct dpu_drm_pix_ext_v1 {
/*
* Number of pixels ext in left, right, top and bottom direction
* for all color components.
*/
int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
/*
* Number of pixels needs to be overfetched in left, right, top
* and bottom directions from source image for scaling.
*/
int32_t left_ftch[DPU_MAX_PLANES];
int32_t right_ftch[DPU_MAX_PLANES];
int32_t top_ftch[DPU_MAX_PLANES];
int32_t btm_ftch[DPU_MAX_PLANES];
/*
* Number of pixels needs to be repeated in left, right, top and
* bottom directions for scaling.
*/
int32_t left_rpt[DPU_MAX_PLANES];
int32_t right_rpt[DPU_MAX_PLANES];
int32_t top_rpt[DPU_MAX_PLANES];
int32_t btm_rpt[DPU_MAX_PLANES];
};
/**
* struct dpu_drm_de_v1 - version 1 of detail enhancer structure
* @enable: Enables/disables detail enhancer
* @sharpen_level1: Sharpening strength for noise
* @sharpen_level2: Sharpening strength for context
* @clip: Clip coefficient
* @limit: Detail enhancer limit factor
* @thr_quiet: Quite zone threshold
* @thr_dieout: Die-out zone threshold
* @thr_low: Linear zone left threshold
* @thr_high: Linear zone right threshold
* @prec_shift: Detail enhancer precision
* @adjust_a: Mapping curves A coefficients
* @adjust_b: Mapping curves B coefficients
* @adjust_c: Mapping curves C coefficients
*/
struct dpu_drm_de_v1 {
uint32_t enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[DPU_MAX_DE_CURVES];
int16_t adjust_b[DPU_MAX_DE_CURVES];
int16_t adjust_c[DPU_MAX_DE_CURVES];
};
/**
* struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
* @enable: Scaler enable
* @dir_en: Detail enhancer enable
* @pe: Pixel extension settings
* @horz_decimate: Horizontal decimation factor
* @vert_decimate: Vertical decimation factor
* @init_phase_x: Initial scaler phase values for x
* @phase_step_x: Phase step values for x
* @init_phase_y: Initial scaler phase values for y
* @phase_step_y: Phase step values for y
* @preload_x: Horizontal preload value
* @preload_y: Vertical preload value
* @src_width: Source width
* @src_height: Source height
* @dst_width: Destination width
* @dst_height: Destination height
* @y_rgb_filter_cfg: Y/RGB plane filter configuration
* @uv_filter_cfg: UV plane filter configuration
* @alpha_filter_cfg: Alpha filter configuration
* @blend_cfg: Selection of blend coefficients
* @lut_flag: LUT configuration flags
* @dir_lut_idx: 2d 4x4 LUT index
* @y_rgb_cir_lut_idx: Y/RGB circular LUT index
* @uv_cir_lut_idx: UV circular LUT index
* @y_rgb_sep_lut_idx: Y/RGB separable LUT index
* @uv_sep_lut_idx: UV separable LUT index
* @de: Detail enhancer settings
*/
struct dpu_drm_scaler_v2 {
/*
* General definitions
*/
uint32_t enable;
uint32_t dir_en;
/*
* Pix ext settings
*/
struct dpu_drm_pix_ext_v1 pe;
/*
* Decimation settings
*/
uint32_t horz_decimate;
uint32_t vert_decimate;
/*
* Phase settings
*/
int32_t init_phase_x[DPU_MAX_PLANES];
int32_t phase_step_x[DPU_MAX_PLANES];
int32_t init_phase_y[DPU_MAX_PLANES];
int32_t phase_step_y[DPU_MAX_PLANES];
uint32_t preload_x[DPU_MAX_PLANES];
uint32_t preload_y[DPU_MAX_PLANES];
uint32_t src_width[DPU_MAX_PLANES];
uint32_t src_height[DPU_MAX_PLANES];
uint32_t dst_width;
uint32_t dst_height;
uint32_t y_rgb_filter_cfg;
uint32_t uv_filter_cfg;
uint32_t alpha_filter_cfg;
uint32_t blend_cfg;
uint32_t lut_flag;
uint32_t dir_lut_idx;
/* for Y(RGB) and UV planes*/
uint32_t y_rgb_cir_lut_idx;
uint32_t uv_cir_lut_idx;
uint32_t y_rgb_sep_lut_idx;
uint32_t uv_sep_lut_idx;
/*
* Detail enhancer settings
*/
struct dpu_drm_de_v1 de;
};
u32 *dpu_hw_util_get_log_mask_ptr(void);
void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
u32 reg_off,
u32 val,
const char *name);
int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
#define DPU_REG_READ(c, off) dpu_reg_read(c, off)
void *dpu_hw_util_get_dir(void);
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
const struct dpu_format *format);
u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
u32 scaler_offset);
void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
u32 csc_reg_off,
struct dpu_csc_cfg *data, bool csc10);
#endif /* _DPU_HW_UTIL_H */
|
