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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_DMA_MACRO_REGS_H_
#define ASIC_REG_DMA_MACRO_REGS_H_
/*
*****************************************
* DMA_MACRO (Prototype: DMA_MACRO)
*****************************************
*/
#define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK 0x4B0000
#define mmDMA_MACRO_LBW_RANGE_MASK_0 0x4B0004
#define mmDMA_MACRO_LBW_RANGE_MASK_1 0x4B0008
#define mmDMA_MACRO_LBW_RANGE_MASK_2 0x4B000C
#define mmDMA_MACRO_LBW_RANGE_MASK_3 0x4B0010
#define mmDMA_MACRO_LBW_RANGE_MASK_4 0x4B0014
#define mmDMA_MACRO_LBW_RANGE_MASK_5 0x4B0018
#define mmDMA_MACRO_LBW_RANGE_MASK_6 0x4B001C
#define mmDMA_MACRO_LBW_RANGE_MASK_7 0x4B0020
#define mmDMA_MACRO_LBW_RANGE_MASK_8 0x4B0024
#define mmDMA_MACRO_LBW_RANGE_MASK_9 0x4B0028
#define mmDMA_MACRO_LBW_RANGE_MASK_10 0x4B002C
#define mmDMA_MACRO_LBW_RANGE_MASK_11 0x4B0030
#define mmDMA_MACRO_LBW_RANGE_MASK_12 0x4B0034
#define mmDMA_MACRO_LBW_RANGE_MASK_13 0x4B0038
#define mmDMA_MACRO_LBW_RANGE_MASK_14 0x4B003C
#define mmDMA_MACRO_LBW_RANGE_MASK_15 0x4B0040
#define mmDMA_MACRO_LBW_RANGE_BASE_0 0x4B0044
#define mmDMA_MACRO_LBW_RANGE_BASE_1 0x4B0048
#define mmDMA_MACRO_LBW_RANGE_BASE_2 0x4B004C
#define mmDMA_MACRO_LBW_RANGE_BASE_3 0x4B0050
#define mmDMA_MACRO_LBW_RANGE_BASE_4 0x4B0054
#define mmDMA_MACRO_LBW_RANGE_BASE_5 0x4B0058
#define mmDMA_MACRO_LBW_RANGE_BASE_6 0x4B005C
#define mmDMA_MACRO_LBW_RANGE_BASE_7 0x4B0060
#define mmDMA_MACRO_LBW_RANGE_BASE_8 0x4B0064
#define mmDMA_MACRO_LBW_RANGE_BASE_9 0x4B0068
#define mmDMA_MACRO_LBW_RANGE_BASE_10 0x4B006C
#define mmDMA_MACRO_LBW_RANGE_BASE_11 0x4B0070
#define mmDMA_MACRO_LBW_RANGE_BASE_12 0x4B0074
#define mmDMA_MACRO_LBW_RANGE_BASE_13 0x4B0078
#define mmDMA_MACRO_LBW_RANGE_BASE_14 0x4B007C
#define mmDMA_MACRO_LBW_RANGE_BASE_15 0x4B0080
#define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK 0x4B0084
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0 0x4B00A8
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1 0x4B00AC
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2 0x4B00B0
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3 0x4B00B4
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4 0x4B00B8
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5 0x4B00BC
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6 0x4B00C0
#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_7 0x4B00C4
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_0 0x4B00C8
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_1 0x4B00CC
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_2 0x4B00D0
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_3 0x4B00D4
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_4 0x4B00D8
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_5 0x4B00DC
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_6 0x4B00E0
#define mmDMA_MACRO_HBW_RANGE_MASK_31_0_7 0x4B00E4
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_0 0x4B00E8
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_1 0x4B00EC
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_2 0x4B00F0
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_3 0x4B00F4
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_4 0x4B00F8
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_5 0x4B00FC
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_6 0x4B0100
#define mmDMA_MACRO_HBW_RANGE_BASE_49_32_7 0x4B0104
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_0 0x4B0108
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_1 0x4B010C
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_2 0x4B0110
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_3 0x4B0114
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_4 0x4B0118
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_5 0x4B011C
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_6 0x4B0120
#define mmDMA_MACRO_HBW_RANGE_BASE_31_0_7 0x4B0124
#define mmDMA_MACRO_WRITE_EN 0x4B0128
#define mmDMA_MACRO_WRITE_CREDIT 0x4B012C
#define mmDMA_MACRO_READ_EN 0x4B0130
#define mmDMA_MACRO_READ_CREDIT 0x4B0134
#define mmDMA_MACRO_SRAM_BUSY 0x4B0138
#define mmDMA_MACRO_RAZWI_LBW_WT_VLD 0x4B013C
#define mmDMA_MACRO_RAZWI_LBW_WT_ID 0x4B0140
#define mmDMA_MACRO_RAZWI_LBW_RD_VLD 0x4B0144
#define mmDMA_MACRO_RAZWI_LBW_RD_ID 0x4B0148
#define mmDMA_MACRO_RAZWI_HBW_WT_VLD 0x4B014C
#define mmDMA_MACRO_RAZWI_HBW_WT_ID 0x4B0150
#define mmDMA_MACRO_RAZWI_HBW_RD_VLD 0x4B0154
#define mmDMA_MACRO_RAZWI_HBW_RD_ID 0x4B0158
#endif /* ASIC_REG_DMA_MACRO_REGS_H_ */
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