drivers/misc/habanalabs/include/goya/asic_reg/mme1_rtr_regs.h


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2018 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_MME1_RTR_REGS_H_
#define ASIC_REG_MME1_RTR_REGS_H_

/*
 *****************************************
 *   MME1_RTR (Prototype: MME_RTR)
 *****************************************
 */

#define mmMME1_RTR_HBW_RD_RQ_E_ARB                                   0x40100

#define mmMME1_RTR_HBW_RD_RQ_W_ARB                                   0x40104

#define mmMME1_RTR_HBW_RD_RQ_N_ARB                                   0x40108

#define mmMME1_RTR_HBW_RD_RQ_S_ARB                                   0x4010C

#define mmMME1_RTR_HBW_RD_RQ_L_ARB                                   0x40110

#define mmMME1_RTR_HBW_E_ARB_MAX                                     0x40120

#define mmMME1_RTR_HBW_W_ARB_MAX                                     0x40124

#define mmMME1_RTR_HBW_N_ARB_MAX                                     0x40128

#define mmMME1_RTR_HBW_S_ARB_MAX                                     0x4012C

#define mmMME1_RTR_HBW_L_ARB_MAX                                     0x40130

#define mmMME1_RTR_HBW_RD_RS_MAX_CREDIT                              0x40140

#define mmMME1_RTR_HBW_WR_RQ_MAX_CREDIT                              0x40144

#define mmMME1_RTR_HBW_RD_RQ_MAX_CREDIT                              0x40148

#define mmMME1_RTR_HBW_RD_RS_E_ARB                                   0x40150

#define mmMME1_RTR_HBW_RD_RS_W_ARB                                   0x40154

#define mmMME1_RTR_HBW_RD_RS_N_ARB                                   0x40158

#define mmMME1_RTR_HBW_RD_RS_S_ARB                                   0x4015C

#define mmMME1_RTR_HBW_RD_RS_L_ARB                                   0x40160

#define mmMME1_RTR_HBW_WR_RQ_E_ARB                                   0x40170

#define mmMME1_RTR_HBW_WR_RQ_W_ARB                                   0x40174

#define mmMME1_RTR_HBW_WR_RQ_N_ARB                                   0x40178

#define mmMME1_RTR_HBW_WR_RQ_S_ARB                                   0x4017C

#define mmMME1_RTR_HBW_WR_RQ_L_ARB                                   0x40180

#define mmMME1_RTR_HBW_WR_RS_E_ARB                                   0x40190

#define mmMME1_RTR_HBW_WR_RS_W_ARB                                   0x40194

#define mmMME1_RTR_HBW_WR_RS_N_ARB                                   0x40198

#define mmMME1_RTR_HBW_WR_RS_S_ARB                                   0x4019C

#define mmMME1_RTR_HBW_WR_RS_L_ARB                                   0x401A0

#define mmMME1_RTR_LBW_RD_RQ_E_ARB                                   0x40200

#define mmMME1_RTR_LBW_RD_RQ_W_ARB                                   0x40204

#define mmMME1_RTR_LBW_RD_RQ_N_ARB                                   0x40208

#define mmMME1_RTR_LBW_RD_RQ_S_ARB                                   0x4020C

#define mmMME1_RTR_LBW_RD_RQ_L_ARB                                   0x40210

#define mmMME1_RTR_LBW_E_ARB_MAX                                     0x40220

#define mmMME1_RTR_LBW_W_ARB_MAX                                     0x40224

#define mmMME1_RTR_LBW_N_ARB_MAX                                     0x40228

#define mmMME1_RTR_LBW_S_ARB_MAX                                     0x4022C

#define mmMME1_RTR_LBW_L_ARB_MAX                                     0x40230

#define mmMME1_RTR_LBW_SRAM_MAX_CREDIT                               0x40240

#define mmMME1_RTR_LBW_RD_RS_E_ARB                                   0x40250

#define mmMME1_RTR_LBW_RD_RS_W_ARB                                   0x40254

#define mmMME1_RTR_LBW_RD_RS_N_ARB                                   0x40258

#define mmMME1_RTR_LBW_RD_RS_S_ARB                                   0x4025C

#define mmMME1_RTR_LBW_RD_RS_L_ARB                                   0x40260

#define mmMME1_RTR_LBW_WR_RQ_E_ARB                                   0x40270

#define mmMME1_RTR_LBW_WR_RQ_W_ARB                                   0x40274

#define mmMME1_RTR_LBW_WR_RQ_N_ARB                                   0x40278

#define mmMME1_RTR_LBW_WR_RQ_S_ARB                                   0x4027C

#define mmMME1_RTR_LBW_WR_RQ_L_ARB                                   0x40280

#define mmMME1_RTR_LBW_WR_RS_E_ARB                                   0x40290

#define mmMME1_RTR_LBW_WR_RS_W_ARB                                   0x40294

#define mmMME1_RTR_LBW_WR_RS_N_ARB                                   0x40298

#define mmMME1_RTR_LBW_WR_RS_S_ARB                                   0x4029C

#define mmMME1_RTR_LBW_WR_RS_L_ARB                                   0x402A0

#define mmMME1_RTR_DBG_E_ARB                                         0x40300

#define mmMME1_RTR_DBG_W_ARB                                         0x40304

#define mmMME1_RTR_DBG_N_ARB                                         0x40308

#define mmMME1_RTR_DBG_S_ARB                                         0x4030C

#define mmMME1_RTR_DBG_L_ARB                                         0x40310

#define mmMME1_RTR_DBG_E_ARB_MAX                                     0x40320

#define mmMME1_RTR_DBG_W_ARB_MAX                                     0x40324

#define mmMME1_RTR_DBG_N_ARB_MAX                                     0x40328

#define mmMME1_RTR_DBG_S_ARB_MAX                                     0x4032C

#define mmMME1_RTR_DBG_L_ARB_MAX                                     0x40330

#define mmMME1_RTR_SPLIT_COEF_0                                      0x40400

#define mmMME1_RTR_SPLIT_COEF_1                                      0x40404

#define mmMME1_RTR_SPLIT_COEF_2                                      0x40408

#define mmMME1_RTR_SPLIT_COEF_3                                      0x4040C

#define mmMME1_RTR_SPLIT_COEF_4                                      0x40410

#define mmMME1_RTR_SPLIT_COEF_5                                      0x40414

#define mmMME1_RTR_SPLIT_COEF_6                                      0x40418

#define mmMME1_RTR_SPLIT_COEF_7                                      0x4041C

#define mmMME1_RTR_SPLIT_COEF_8                                      0x40420

#define mmMME1_RTR_SPLIT_COEF_9                                      0x40424

#define mmMME1_RTR_SPLIT_CFG                                         0x40440

#define mmMME1_RTR_SPLIT_RD_SAT                                      0x40444

#define mmMME1_RTR_SPLIT_RD_RST_TOKEN                                0x40448

#define mmMME1_RTR_SPLIT_RD_TIMEOUT_0                                0x4044C

#define mmMME1_RTR_SPLIT_RD_TIMEOUT_1                                0x40450

#define mmMME1_RTR_SPLIT_WR_SAT                                      0x40454

#define mmMME1_RTR_WPLIT_WR_TST_TOLEN                                0x40458

#define mmMME1_RTR_SPLIT_WR_TIMEOUT_0                                0x4045C

#define mmMME1_RTR_SPLIT_WR_TIMEOUT_1                                0x40460

#define mmMME1_RTR_HBW_RANGE_HIT                                     0x40470

#define mmMME1_RTR_HBW_RANGE_MASK_L_0                                0x40480

#define mmMME1_RTR_HBW_RANGE_MASK_L_1                                0x40484

#define mmMME1_RTR_HBW_RANGE_MASK_L_2                                0x40488

#define mmMME1_RTR_HBW_RANGE_MASK_L_3                                0x4048C

#define mmMME1_RTR_HBW_RANGE_MASK_L_4                                0x40490

#define mmMME1_RTR_HBW_RANGE_MASK_L_5                                0x40494

#define mmMME1_RTR_HBW_RANGE_MASK_L_6                                0x40498

#define mmMME1_RTR_HBW_RANGE_MASK_L_7                                0x4049C

#define mmMME1_RTR_HBW_RANGE_MASK_H_0                                0x404A0

#define mmMME1_RTR_HBW_RANGE_MASK_H_1                                0x404A4

#define mmMME1_RTR_HBW_RANGE_MASK_H_2                                0x404A8

#define mmMME1_RTR_HBW_RANGE_MASK_H_3                                0x404AC

#define mmMME1_RTR_HBW_RANGE_MASK_H_4                                0x404B0

#define mmMME1_RTR_HBW_RANGE_MASK_H_5                                0x404B4

#define mmMME1_RTR_HBW_RANGE_MASK_H_6                                0x404B8

#define mmMME1_RTR_HBW_RANGE_MASK_H_7                                0x404BC

#define mmMME1_RTR_HBW_RANGE_BASE_L_0                                0x404C0

#define mmMME1_RTR_HBW_RANGE_BASE_L_1                                0x404C4

#define mmMME1_RTR_HBW_RANGE_BASE_L_2                                0x404C8

#define mmMME1_RTR_HBW_RANGE_BASE_L_3                                0x404CC

#define mmMME1_RTR_HBW_RANGE_BASE_L_4                                0x404D0

#define mmMME1_RTR_HBW_RANGE_BASE_L_5                                0x404D4

#define mmMME1_RTR_HBW_RANGE_BASE_L_6                                0x404D8

#define mmMME1_RTR_HBW_RANGE_BASE_L_7                                0x404DC

#define mmMME1_RTR_HBW_RANGE_BASE_H_0                                0x404E0

#define mmMME1_RTR_HBW_RANGE_BASE_H_1                                0x404E4

#define mmMME1_RTR_HBW_RANGE_BASE_H_2                                0x404E8

#define mmMME1_RTR_HBW_RANGE_BASE_H_3                                0x404EC

#define mmMME1_RTR_HBW_RANGE_BASE_H_4                                0x404F0

#define mmMME1_RTR_HBW_RANGE_BASE_H_5                                0x404F4

#define mmMME1_RTR_HBW_RANGE_BASE_H_6                                0x404F8

#define mmMME1_RTR_HBW_RANGE_BASE_H_7                                0x404FC

#define mmMME1_RTR_LBW_RANGE_HIT                                     0x40500

#define mmMME1_RTR_LBW_RANGE_MASK_0                                  0x40510

#define mmMME1_RTR_LBW_RANGE_MASK_1                                  0x40514

#define mmMME1_RTR_LBW_RANGE_MASK_2                                  0x40518

#define mmMME1_RTR_LBW_RANGE_MASK_3                                  0x4051C

#define mmMME1_RTR_LBW_RANGE_MASK_4                                  0x40520

#define mmMME1_RTR_LBW_RANGE_MASK_5                                  0x40524

#define mmMME1_RTR_LBW_RANGE_MASK_6                                  0x40528

#define mmMME1_RTR_LBW_RANGE_MASK_7                                  0x4052C

#define mmMME1_RTR_LBW_RANGE_MASK_8                                  0x40530

#define mmMME1_RTR_LBW_RANGE_MASK_9                                  0x40534

#define mmMME1_RTR_LBW_RANGE_MASK_10                                 0x40538

#define mmMME1_RTR_LBW_RANGE_MASK_11                                 0x4053C

#define mmMME1_RTR_LBW_RANGE_MASK_12                                 0x40540

#define mmMME1_RTR_LBW_RANGE_MASK_13                                 0x40544

#define mmMME1_RTR_LBW_RANGE_MASK_14                                 0x40548

#define mmMME1_RTR_LBW_RANGE_MASK_15                                 0x4054C

#define mmMME1_RTR_LBW_RANGE_BASE_0                                  0x40550

#define mmMME1_RTR_LBW_RANGE_BASE_1                                  0x40554

#define mmMME1_RTR_LBW_RANGE_BASE_2                                  0x40558

#define mmMME1_RTR_LBW_RANGE_BASE_3                                  0x4055C

#define mmMME1_RTR_LBW_RANGE_BASE_4                                  0x40560

#define mmMME1_RTR_LBW_RANGE_BASE_5                                  0x40564

#define mmMME1_RTR_LBW_RANGE_BASE_6                                  0x40568

#define mmMME1_RTR_LBW_RANGE_BASE_7                                  0x4056C

#define mmMME1_RTR_LBW_RANGE_BASE_8                                  0x40570

#define mmMME1_RTR_LBW_RANGE_BASE_9                                  0x40574

#define mmMME1_RTR_LBW_RANGE_BASE_10                                 0x40578

#define mmMME1_RTR_LBW_RANGE_BASE_11                                 0x4057C

#define mmMME1_RTR_LBW_RANGE_BASE_12                                 0x40580

#define mmMME1_RTR_LBW_RANGE_BASE_13                                 0x40584

#define mmMME1_RTR_LBW_RANGE_BASE_14                                 0x40588

#define mmMME1_RTR_LBW_RANGE_BASE_15                                 0x4058C

#define mmMME1_RTR_RGLTR                                             0x40590

#define mmMME1_RTR_RGLTR_WR_RESULT                                   0x40594

#define mmMME1_RTR_RGLTR_RD_RESULT                                   0x40598

#define mmMME1_RTR_SCRAMB_EN                                         0x40600

#define mmMME1_RTR_NON_LIN_SCRAMB                                    0x40604

#endif /* ASIC_REG_MME1_RTR_REGS_H_ */