blob: 7f86621179a55519ed862a7393543e25de4487bb (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
|
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_TPC0_NRTR_MASKS_H_
#define ASIC_REG_TPC0_NRTR_MASKS_H_
/*
*****************************************
* TPC0_NRTR (Prototype: IF_NRTR)
*****************************************
*/
/* TPC0_NRTR_HBW_MAX_CRED */
#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
#define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8
#define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16
#define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24
#define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
/* TPC0_NRTR_LBW_MAX_CRED */
#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
#define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8
#define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16
#define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24
#define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
/* TPC0_NRTR_DBG_E_ARB */
#define TPC0_NRTR_DBG_E_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_E_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_E_ARB_S_SHIFT 8
#define TPC0_NRTR_DBG_E_ARB_S_MASK 0x700
#define TPC0_NRTR_DBG_E_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_E_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_E_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_E_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_W_ARB */
#define TPC0_NRTR_DBG_W_ARB_E_SHIFT 0
#define TPC0_NRTR_DBG_W_ARB_E_MASK 0x7
#define TPC0_NRTR_DBG_W_ARB_S_SHIFT 8
#define TPC0_NRTR_DBG_W_ARB_S_MASK 0x700
#define TPC0_NRTR_DBG_W_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_W_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_W_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_W_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_N_ARB */
#define TPC0_NRTR_DBG_N_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_N_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_N_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_N_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_N_ARB_S_SHIFT 16
#define TPC0_NRTR_DBG_N_ARB_S_MASK 0x70000
#define TPC0_NRTR_DBG_N_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_N_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_S_ARB */
#define TPC0_NRTR_DBG_S_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_S_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_S_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_S_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_S_ARB_N_SHIFT 16
#define TPC0_NRTR_DBG_S_ARB_N_MASK 0x70000
#define TPC0_NRTR_DBG_S_ARB_L_SHIFT 24
#define TPC0_NRTR_DBG_S_ARB_L_MASK 0x7000000
/* TPC0_NRTR_DBG_L_ARB */
#define TPC0_NRTR_DBG_L_ARB_W_SHIFT 0
#define TPC0_NRTR_DBG_L_ARB_W_MASK 0x7
#define TPC0_NRTR_DBG_L_ARB_E_SHIFT 8
#define TPC0_NRTR_DBG_L_ARB_E_MASK 0x700
#define TPC0_NRTR_DBG_L_ARB_S_SHIFT 16
#define TPC0_NRTR_DBG_L_ARB_S_MASK 0x70000
#define TPC0_NRTR_DBG_L_ARB_N_SHIFT 24
#define TPC0_NRTR_DBG_L_ARB_N_MASK 0x7000000
/* TPC0_NRTR_DBG_E_ARB_MAX */
#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_W_ARB_MAX */
#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_N_ARB_MAX */
#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_S_ARB_MAX */
#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_DBG_L_ARB_MAX */
#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0
#define TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F
/* TPC0_NRTR_SPLIT_COEF */
#define TPC0_NRTR_SPLIT_COEF_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF
/* TPC0_NRTR_SPLIT_CFG */
#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0
#define TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1
#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1
#define TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2
#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2
#define TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC
#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4
#define TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10
#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5
#define TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20
#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6
#define TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0
/* TPC0_NRTR_SPLIT_RD_SAT */
#define TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF
/* TPC0_NRTR_SPLIT_RD_RST_TOKEN */
#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF
/* TPC0_NRTR_SPLIT_RD_TIMEOUT */
#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF
/* TPC0_NRTR_SPLIT_WR_SAT */
#define TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF
/* TPC0_NRTR_WPLIT_WR_TST_TOLEN */
#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0
#define TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF
/* TPC0_NRTR_SPLIT_WR_TIMEOUT */
#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0
#define TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF
/* TPC0_NRTR_HBW_RANGE_HIT */
#define TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT 0
#define TPC0_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF
/* TPC0_NRTR_HBW_RANGE_MASK_L */
#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0
#define TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF
/* TPC0_NRTR_HBW_RANGE_MASK_H */
#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0
#define TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF
/* TPC0_NRTR_HBW_RANGE_BASE_L */
#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0
#define TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF
/* TPC0_NRTR_HBW_RANGE_BASE_H */
#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0
#define TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF
/* TPC0_NRTR_LBW_RANGE_HIT */
#define TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT 0
#define TPC0_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF
/* TPC0_NRTR_LBW_RANGE_MASK */
#define TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0
#define TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF
/* TPC0_NRTR_LBW_RANGE_BASE */
#define TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0
#define TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF
/* TPC0_NRTR_RGLTR */
#define TPC0_NRTR_RGLTR_WR_EN_SHIFT 0
#define TPC0_NRTR_RGLTR_WR_EN_MASK 0x1
#define TPC0_NRTR_RGLTR_RD_EN_SHIFT 4
#define TPC0_NRTR_RGLTR_RD_EN_MASK 0x10
/* TPC0_NRTR_RGLTR_WR_RESULT */
#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0
#define TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF
/* TPC0_NRTR_RGLTR_RD_RESULT */
#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0
#define TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF
/* TPC0_NRTR_SCRAMB_EN */
#define TPC0_NRTR_SCRAMB_EN_VAL_SHIFT 0
#define TPC0_NRTR_SCRAMB_EN_VAL_MASK 0x1
/* TPC0_NRTR_NON_LIN_SCRAMB */
#define TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0
#define TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1
#endif /* ASIC_REG_TPC0_NRTR_MASKS_H_ */
|
