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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_TPC4_CMDQ_REGS_H_
#define ASIC_REG_TPC4_CMDQ_REGS_H_
/*
*****************************************
* TPC4_CMDQ (Prototype: CMDQ)
*****************************************
*/
#define mmTPC4_CMDQ_GLBL_CFG0 0xF09000
#define mmTPC4_CMDQ_GLBL_CFG1 0xF09004
#define mmTPC4_CMDQ_GLBL_PROT 0xF09008
#define mmTPC4_CMDQ_GLBL_ERR_CFG 0xF0900C
#define mmTPC4_CMDQ_GLBL_ERR_ADDR_LO 0xF09010
#define mmTPC4_CMDQ_GLBL_ERR_ADDR_HI 0xF09014
#define mmTPC4_CMDQ_GLBL_ERR_WDATA 0xF09018
#define mmTPC4_CMDQ_GLBL_SECURE_PROPS 0xF0901C
#define mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS 0xF09020
#define mmTPC4_CMDQ_GLBL_STS0 0xF09024
#define mmTPC4_CMDQ_GLBL_STS1 0xF09028
#define mmTPC4_CMDQ_CQ_CFG0 0xF090B0
#define mmTPC4_CMDQ_CQ_CFG1 0xF090B4
#define mmTPC4_CMDQ_CQ_ARUSER 0xF090B8
#define mmTPC4_CMDQ_CQ_PTR_LO 0xF090C0
#define mmTPC4_CMDQ_CQ_PTR_HI 0xF090C4
#define mmTPC4_CMDQ_CQ_TSIZE 0xF090C8
#define mmTPC4_CMDQ_CQ_CTL 0xF090CC
#define mmTPC4_CMDQ_CQ_PTR_LO_STS 0xF090D4
#define mmTPC4_CMDQ_CQ_PTR_HI_STS 0xF090D8
#define mmTPC4_CMDQ_CQ_TSIZE_STS 0xF090DC
#define mmTPC4_CMDQ_CQ_CTL_STS 0xF090E0
#define mmTPC4_CMDQ_CQ_STS0 0xF090E4
#define mmTPC4_CMDQ_CQ_STS1 0xF090E8
#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN 0xF090F0
#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF090F4
#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT 0xF090F8
#define mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF090FC
#define mmTPC4_CMDQ_CQ_IFIFO_CNT 0xF09108
#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF09120
#define mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF09124
#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF09128
#define mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF0912C
#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF09130
#define mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF09134
#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF09138
#define mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF0913C
#define mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF09140
#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF09144
#define mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF09148
#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF0914C
#define mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF09150
#define mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF09154
#define mmTPC4_CMDQ_CP_FENCE0_RDATA 0xF09158
#define mmTPC4_CMDQ_CP_FENCE1_RDATA 0xF0915C
#define mmTPC4_CMDQ_CP_FENCE2_RDATA 0xF09160
#define mmTPC4_CMDQ_CP_FENCE3_RDATA 0xF09164
#define mmTPC4_CMDQ_CP_FENCE0_CNT 0xF09168
#define mmTPC4_CMDQ_CP_FENCE1_CNT 0xF0916C
#define mmTPC4_CMDQ_CP_FENCE2_CNT 0xF09170
#define mmTPC4_CMDQ_CP_FENCE3_CNT 0xF09174
#define mmTPC4_CMDQ_CP_STS 0xF09178
#define mmTPC4_CMDQ_CP_CURRENT_INST_LO 0xF0917C
#define mmTPC4_CMDQ_CP_CURRENT_INST_HI 0xF09180
#define mmTPC4_CMDQ_CP_BARRIER_CFG 0xF09184
#define mmTPC4_CMDQ_CP_DBG_0 0xF09188
#define mmTPC4_CMDQ_CQ_BUF_ADDR 0xF09308
#define mmTPC4_CMDQ_CQ_BUF_RDATA 0xF0930C
#endif /* ASIC_REG_TPC4_CMDQ_REGS_H_ */
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