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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2018 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_TPC5_CMDQ_REGS_H_
#define ASIC_REG_TPC5_CMDQ_REGS_H_
/*
*****************************************
* TPC5_CMDQ (Prototype: CMDQ)
*****************************************
*/
#define mmTPC5_CMDQ_GLBL_CFG0 0xF49000
#define mmTPC5_CMDQ_GLBL_CFG1 0xF49004
#define mmTPC5_CMDQ_GLBL_PROT 0xF49008
#define mmTPC5_CMDQ_GLBL_ERR_CFG 0xF4900C
#define mmTPC5_CMDQ_GLBL_ERR_ADDR_LO 0xF49010
#define mmTPC5_CMDQ_GLBL_ERR_ADDR_HI 0xF49014
#define mmTPC5_CMDQ_GLBL_ERR_WDATA 0xF49018
#define mmTPC5_CMDQ_GLBL_SECURE_PROPS 0xF4901C
#define mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS 0xF49020
#define mmTPC5_CMDQ_GLBL_STS0 0xF49024
#define mmTPC5_CMDQ_GLBL_STS1 0xF49028
#define mmTPC5_CMDQ_CQ_CFG0 0xF490B0
#define mmTPC5_CMDQ_CQ_CFG1 0xF490B4
#define mmTPC5_CMDQ_CQ_ARUSER 0xF490B8
#define mmTPC5_CMDQ_CQ_PTR_LO 0xF490C0
#define mmTPC5_CMDQ_CQ_PTR_HI 0xF490C4
#define mmTPC5_CMDQ_CQ_TSIZE 0xF490C8
#define mmTPC5_CMDQ_CQ_CTL 0xF490CC
#define mmTPC5_CMDQ_CQ_PTR_LO_STS 0xF490D4
#define mmTPC5_CMDQ_CQ_PTR_HI_STS 0xF490D8
#define mmTPC5_CMDQ_CQ_TSIZE_STS 0xF490DC
#define mmTPC5_CMDQ_CQ_CTL_STS 0xF490E0
#define mmTPC5_CMDQ_CQ_STS0 0xF490E4
#define mmTPC5_CMDQ_CQ_STS1 0xF490E8
#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN 0xF490F0
#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xF490F4
#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT 0xF490F8
#define mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT 0xF490FC
#define mmTPC5_CMDQ_CQ_IFIFO_CNT 0xF49108
#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO 0xF49120
#define mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI 0xF49124
#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO 0xF49128
#define mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI 0xF4912C
#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO 0xF49130
#define mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI 0xF49134
#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO 0xF49138
#define mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI 0xF4913C
#define mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET 0xF49140
#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xF49144
#define mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xF49148
#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xF4914C
#define mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xF49150
#define mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET 0xF49154
#define mmTPC5_CMDQ_CP_FENCE0_RDATA 0xF49158
#define mmTPC5_CMDQ_CP_FENCE1_RDATA 0xF4915C
#define mmTPC5_CMDQ_CP_FENCE2_RDATA 0xF49160
#define mmTPC5_CMDQ_CP_FENCE3_RDATA 0xF49164
#define mmTPC5_CMDQ_CP_FENCE0_CNT 0xF49168
#define mmTPC5_CMDQ_CP_FENCE1_CNT 0xF4916C
#define mmTPC5_CMDQ_CP_FENCE2_CNT 0xF49170
#define mmTPC5_CMDQ_CP_FENCE3_CNT 0xF49174
#define mmTPC5_CMDQ_CP_STS 0xF49178
#define mmTPC5_CMDQ_CP_CURRENT_INST_LO 0xF4917C
#define mmTPC5_CMDQ_CP_CURRENT_INST_HI 0xF49180
#define mmTPC5_CMDQ_CP_BARRIER_CFG 0xF49184
#define mmTPC5_CMDQ_CP_DBG_0 0xF49188
#define mmTPC5_CMDQ_CQ_BUF_ADDR 0xF49308
#define mmTPC5_CMDQ_CQ_BUF_RDATA 0xF4930C
#endif /* ASIC_REG_TPC5_CMDQ_REGS_H_ */
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