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// SPDX-License-Identifier: GPL-2.0
/* Marvell OcteonTx2 CGX driver
*
* Copyright (C) 2018 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "cgx.h"
#define DRV_NAME "octeontx2-cgx"
#define DRV_STRING "Marvell OcteonTX2 CGX/MAC Driver"
struct cgx {
void __iomem *reg_base;
struct pci_dev *pdev;
u8 cgx_id;
u8 lmac_count;
struct list_head cgx_list;
};
static LIST_HEAD(cgx_list);
/* Supported devices */
static const struct pci_device_id cgx_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
{ 0, } /* end of table */
};
MODULE_DEVICE_TABLE(pci, cgx_id_table);
static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
{
return readq(cgx->reg_base + (lmac << 18) + offset);
}
int cgx_get_cgx_cnt(void)
{
struct cgx *cgx_dev;
int count = 0;
list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
count++;
return count;
}
EXPORT_SYMBOL(cgx_get_cgx_cnt);
int cgx_get_lmac_cnt(void *cgxd)
{
struct cgx *cgx = cgxd;
if (!cgx)
return -ENODEV;
return cgx->lmac_count;
}
EXPORT_SYMBOL(cgx_get_lmac_cnt);
void *cgx_get_pdata(int cgx_id)
{
struct cgx *cgx_dev;
list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
if (cgx_dev->cgx_id == cgx_id)
return cgx_dev;
}
return NULL;
}
EXPORT_SYMBOL(cgx_get_pdata);
static void cgx_lmac_init(struct cgx *cgx)
{
cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7;
if (cgx->lmac_count > MAX_LMAC_PER_CGX)
cgx->lmac_count = MAX_LMAC_PER_CGX;
}
static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
struct cgx *cgx;
int err;
cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
if (!cgx)
return -ENOMEM;
cgx->pdev = pdev;
pci_set_drvdata(pdev, cgx);
err = pci_enable_device(pdev);
if (err) {
dev_err(dev, "Failed to enable PCI device\n");
pci_set_drvdata(pdev, NULL);
return err;
}
err = pci_request_regions(pdev, DRV_NAME);
if (err) {
dev_err(dev, "PCI request regions failed 0x%x\n", err);
goto err_disable_device;
}
/* MAP configuration registers */
cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
if (!cgx->reg_base) {
dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
err = -ENOMEM;
goto err_release_regions;
}
list_add(&cgx->cgx_list, &cgx_list);
cgx->cgx_id = cgx_get_cgx_cnt() - 1;
cgx_lmac_init(cgx);
return 0;
err_release_regions:
list_del(&cgx->cgx_list);
pci_release_regions(pdev);
err_disable_device:
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
return err;
}
static void cgx_remove(struct pci_dev *pdev)
{
struct cgx *cgx = pci_get_drvdata(pdev);
list_del(&cgx->cgx_list);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
struct pci_driver cgx_driver = {
.name = DRV_NAME,
.id_table = cgx_id_table,
.probe = cgx_probe,
.remove = cgx_remove,
};
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